MSC7116_08 Datasheet, PDF (39/60 Pages) Freescale Semiconductor, Inc – Low-Cost 16-bit DSP with DDR Controller and 10/100 Mbps Ethernet MAC

2.5.13 JTAG Signals
Table 31. JTAG Timing
No.
Characteristics
All frequencies
Min
Max
700 TCK frequency of operation (1/(T_C × 3)
0.0
40.0
Note: T_C = 1/CLOCK which is the period of the core clock. The TCK
frequency must less than 1/3 of the core frequency with an absolute
maximum limit of 40 MHz.
701 TCK cycle time
25.0
—
702 TCK clock pulse width measured at V_{M =} 1.6 V
703 TCK rise and fall times
11.0
—
0.0
3.0
704 Boundary scan input data set-up time
5.0
—
705 Boundary scan input data hold time
14.0
—
706 TCK low to output data valid
0.0
20.0
707 TCK low to output high impedance
0.0
20.0
708 TMS, TDI data set-up time
5.0
—
709 TMS, TDI data hold time
14.0
—
710 TCK low to TDO data valid
0.0
24.0
711 TCK low to TDO high impedance
0.0
10.0
712 TRST assert time
100.0
—
Note: All timings apply to OCE module data transfers as the OCE module uses the JTAG port as an interface.
TCK
(Input)
V_IH
703
V_M
V_IL
701
702
V_M
703
Figure 26. Test Clock Input Timing Diagram
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MSC7116 Data Sheet, Rev. 13
Freescale Semiconductor
39