MSC7116_08 Datasheet, PDF (53/60 Pages) Freescale Semiconductor, Inc – Low-Cost 16-bit DSP with DDR Controller and 10/100 Mbps Ethernet MAC

Hardware Design Considerations
When booting from a power-on reset, the HDI16 is additionally configurable as follows:
• 8- or 16-bit mode as specified by the H8BIT pin.
• Data strobe as specified by the HDSP and HDDS pins.
These pins are sampled only on the deassertion of power-on reset. During a boot from a hard reset, the configuration of these
pins is unaffected.
Note: When the HDI16 is used for booting or other purposes, bit 0 is the least significant bit and not the most significant bit
as for other DSP products.
3.4.3.2 I²C Boot
When the MSC7116 device is configured to boot from the I²C port, the boot program configures the GPIO pins for I²C
operation. Then the MSC7116 device initiates accesses to the I²C module, downloading data to the MSC7116 device. The I²C
interface is configured as follows:
• PLL is disabled and bypassed so that the I²C module is clocked with the IPBus clock.
• I²C interface operates in master mode and polling is used.
• EPROM operates in slave mode.
• Clock divider is set to 128.
• Address of slave during boot is 0xA0.
The IPBus clock is internally divided to generate the bit clock, as follows:
• CLKIN must be a maximum of 100 MHz
• PLL is bypassed.
• IPBus clock = CLKIN/2 is a maximum of 50 MHz.
• I²C bit clock must be less than or equal to:
— IPBus clock/I²C clock divider
— 50 MHz (max)/128
— 390.6 KHz
This satisfies the maximum clock rate requirement of 400 kbps for the I²C interface. For details on the boot procedure, see the
“Boot Program” chapter of the MSC711x Reference Manual.
3.4.3.3 SPI Boot
When the MSC7116 device is configured to boot from the SPI port, the boot program configures the GPIO pins for SPI
operation. Then the MSC7116 device initiates accesses to the SPI module, downloading data to the MSC7116 device. When
the SPI routines run in the boot ROM, the MSC7116 is always configured as the SPI master. Booting through the SPI is
supported for serial EEPROM devices and serial Flash devices. When a READ_ID instruction is issued to the serial memory
device and the device returns a value of 0x00 or 0xFF, the routines for accessing a serial EEPROM are used, at a maximum
frequency of 4 Mbps. Otherwise, the routines for accessing a serial Flash are used, and they can run at faster speeds. Booting is
performed through one of two sets of pins:
• Main set: BM[2–3], HA3, and HCS2, which allow use of the PLL.
• Alternate set: UTXD, URXD, SDA, and SCL, which cannot be used with the PLL.
In either configuration, an error during SPI boot is flagged on the EVNT3 pin. For details on the boot procedure, see the “Boot
Program” chapter of the MSC711x Reference Manual.
MSC7116 Data Sheet, Rev. 13
Freescale Semiconductor
53