MSC7116_08 Datasheet, PDF (24/60 Pages) Freescale Semiconductor, Inc – Low-Cost 16-bit DSP with DDR Controller and 10/100 Mbps Ethernet MAC

Electrical Characteristics
2.5.3 Reset Timing
The MSC7116 device has several inputs to the reset logic. All MSC7116 reset sources are fed into the reset controller, which
takes different actions depending on the source of the reset. The reset status register indicates the most recent sources to cause
a reset. Table 14 describes the reset sources.
Name
Power-on reset
(PORESET)
External Hard
reset (HRESET)
Software
watchdog reset
Bus monitor
reset
JTAG EXTEST,
CLAMP, or
HIGHZ command
Direction
Input
Input/ Output
Internal
Internal
Internal
Table 14. Reset Sources
Description
Initiates the power-on reset flow that resets the MSC7116 and configures various attributes of the
MSC7116. On PORESET, the entire MSC7116 device is reset. SPLL and DLL states are reset,
HRESET is driven, the SC1400 extended core is reset, and system configuration is sampled. The
system is configured only when PORESET is asserted.
Initiates the hard reset flow that configures various attributes of the MSC7116. While HRESET is
asserted, HRESET is an open-drain output. Upon hard reset, HRESET is driven and the SC1400
extended core is reset.
When the MSC7116 watchdog count reaches zero, a software watchdog reset is signalled. The
enabled software watchdog event then generates an internal hard reset sequence.
When the MSC7116 bus monitor count reaches zero, a bus monitor hard reset is asserted. The
enabled bus monitor event then generates an internal hard reset sequence.
When a Test Access Port (TAP) executes an EXTEST, CLAMP, or HIGHZ command, the TAP logic
asserts an internal reset signal that generates an internal soft reset sequence.
Table 15 summarizes the reset actions that occur as a result of the different reset sources.
Table 15. Reset Actions for Each Reset Source
Power-On Reset
(PORESET)
Hard Reset
(HRESET)
Soft Reset
(SRESET)
Reset Action/Reset Source
Configuration pins sampled (refer to Section 2.5.3.1 for
details).
PLL and clock synthesis states Reset
HRESET Driven
Software watchdog and bus time-out monitor registers
Clock synthesis modules (STOPCTRL, HLTREQ, and
HLTACK) reset
Extended core reset
Peripheral modules reset
External only
Yes
Yes
Yes
Yes
Yes
Yes
Yes
External or
Internal (Software
Watchdog or Bus
Monitor)
JTAG Command:
EXTEST, CLAMP,
or HIGHZ
No
No
No
No
Yes
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
2.5.3.1 Power-On Reset (PORESET) Pin
Asserting PORESET initiates the power-on reset flow. PORESET must be asserted externally for at least 16 CLKIN cycles after
external power to the MSC7116 reaches at least 2/3 V_DD.
MSC7116 Data Sheet, Rev. 13
24
Freescale Semiconductor