MSC7116_08 Datasheet, PDF (37/60 Pages) Freescale Semiconductor, Inc – Low-Cost 16-bit DSP with DDR Controller and 10/100 Mbps Ethernet MAC

2.5.9 UART Timing
Table 27. UART Timing
No.
Characteristics
— Internal bus clock (APBCLK)
— Internal bus clock period (1/APBCLK)
400 URXD and UTXD inputs high/low duration
401 URXD and UTXD inputs rise/fall time
402 UTXD output rise/fall time
Expression
F_CORE/2
T_APBCLK
16 × T_APBCLK
Min
—
7.52
120.3
—
—
Max
133
—
—
5
5
Unit
MHz
ns
ns
ns
ns
UTXD, URXD
inputs
401
401
400
400
Figure 21. UART Input Timing
402
402
UTXD Output
Figure 22. UART Output Timing
2.5.10 EE Timing
Table 28. EE0 Timing
Number
Characteristics
Type
Min
65
66
Notes: 1.
2.
3.
EE0 input to the core
Asynchronous
4 core clock periods
EE0 output from the core
Synchronous to core clock
1 core clock period
The core clock is the SC1400 core clock. The ratio between the core clock and CLKOUT is configured during power-on-reset.
Configure the direction of the EE pin in the EE_CTRL register (see the SC140/SC1400 Core Reference Manual for details.
Refer to Table 1-11 on page 1-16 for details on EE pin functionality.
Figure 24 shows the signal behavior of the EE pin.
EE0 In
EE0 Out
65
66
Figure 23. EE Pin Timing
MSC7116 Data Sheet, Rev. 13
Freescale Semiconductor
37