MSC7116_08 Datasheet, PDF (54/60 Pages) Freescale Semiconductor, Inc – Low-Cost 16-bit DSP with DDR Controller and 10/100 Mbps Ethernet MAC

Hardware Design Considerations
3.5 DDR Memory System Guidelines
MSC7116 devices contain a memory controller that provides a glueless interface to external double data rate (DDR) SDRAM
memory modules with Class 2 Series Stub Termination Logic 2.5 V (SSTL_2). There are two termination techniques, as shown
in Figure 36. Technique B is the most popular termination technique.
Controller
Address ^SSTL_2
Command
V_TT
RS
DDR
Bank
DDR
Bank
V_TT
Generator
RT
Technique A
Chip Selects ^SSTL_2
Data
RS
Strobes _{SSTL_2}
Mask
VREF
Controller
RS
Address ^SSTL_2
Command
DDR
Bank
RT
DDR
Bank
V_TT
Generator
RT
Technique B
Chip Selects ^SSTL_2
RS
RT
Data
Strobes _{SSTL_2}
Mask
Figure 36. SSTL Termination Techniques
Figure 37 illustrates the power wattage for the resistors. Typical values for the resistors are as follows:
• RS = 22 Ω
• RT = 24 Ω
MSC7116 Data Sheet, Rev. 13
54
Freescale Semiconductor