MSC7116_08 Datasheet, PDF (51/60 Pages) Freescale Semiconductor, Inc – Low-Cost 16-bit DSP with DDR Controller and 10/100 Mbps Ethernet MAC

Hardware Design Considerations
3.3.6 Example Total Power Consumption
Using the examples in this section and assuming four peripherals and 10 I/O lines active, a total power consumption value is
estimated as the following:
P_TOTAL = 287 + (4 × 3.83) + 326.3 + (10 × 7.19) + 64 = 764.52 mW
Eqn. 13
3.4 Reset and Boot
This section describes the recommendations for configuring the MSC7116 at reset and boot.
3.4.1 Reset Circuit
HRESET is a bidirectional signal and, if driven as an input, should be driven with an open collector or open-drain device. For
an open-drain output such as HRESET, take care when driving many buffers that implement input bus-hold circuitry. The
bus-hold currents can cause enough voltage drop across the pull-up resistor to change the logic level to low. Either a smaller
value of pull-up or less current loading from the bus-hold drivers overcomes this issue. To avoid exceeding the MSC7116 output
current, the pull-up value should not be too small (a 1 KΩ pull-up resistor is used in the MSC711xADS reference design).
3.4.2 Reset Configuration Pins
Table 34 shows the MSC7116 reset configuration signals. These signals are sampled at the deassertion (rising edge) of
PORESET. For details, refer to the Reset chapter of the MSC711x Reference Manual.
Table 34. Reset Configuration Signals
Signal
BM[3–0]
SWTE
Description
Determines boot mode.
Determines watchdog functionality.
HDSP
Configures HDI16 strobe polarity.
H8BIT
Configures HDI16 operation mode.
Settings
See Table 35 for details.
0 Watchdog timer disabled.
1 Watchdog timer enabled.
0 Host Data strobes active low.
1 Host Data strobes active high.
0 HDI16 port configured for 16-bit operation.
1 HDI16 port configured for 8-bit operation.
MSC7116 Data Sheet, Rev. 13
Freescale Semiconductor
51