MSC7116_08 Datasheet, PDF (48/60 Pages) Freescale Semiconductor, Inc – Low-Cost 16-bit DSP with DDR Controller and 10/100 Mbps Ethernet MAC

Hardware Design Considerations
3.2.3 Power Planes
Each power supply pin (V_DDC, V_DDM, and V_DDIO) should have a low-impedance path to the board power supply. Each GND pin
should be provided with a low-impedance path to ground. The power supply pins drive distinct groups of logic on the device.
The MSC7116 V_DDC power supply pins should be bypassed to ground using decoupling capacitors. The capacitor leads and
associated printed circuit traces connecting to device power pins and GND should be kept to less than half an inch per capacitor
lead. A minimum four-layer board that employs two inner layers as power and GND planes is recommended. See Section 3.5
for DDR Controller power guidelines.
3.2.4 Decoupling
Both the I/O voltage and core voltage should be decoupled for switching noise. For I/O decoupling, use standard capacitor
values of 0.01 μF for every two to three voltage pins. For core voltage decoupling, use two levels of decoupling. The first level
should consist of a 0.01 µF high frequency capacitor with low effective series resistance (ESR) and effective series inductance
(ESL) for every two to three voltage pins. The second decoupling level should consist of two bulk/tantalum decoupling
capacitors, one 10 μF and one 47 μF, (with low ESR and ESL) mounted as closely as possible to the MSC7116 voltage pins.
Additionally, the maximum drop between the power supply and the DSP device should be 15 mV at 1 A.
3.2.5 PLL Power Supply Filtering
The MSC7116 V_DDPLL power signal provides power to the clock generation PLL. To ensure stability of the internal clock, the
power supplied to this pin should be filtered with capacitors that have low and high frequency filtering characteristics. V_DDPLL
can be connected to V_DDC through a 2 Ω resistor. V_SSPLL can be tied directly to the GND plane. A circuit similar to the one
shown in Figure 35 is recommended. The PLL loop filter should be placed as closely as possible to the V_DDPLL pin (which are
located on the outside edge of the silicon package) to minimize noise coupled from nearby circuits.The 0.01 µF capacitor should
be closest to V_DDPLL, followed by the 0.1 µF capacitor, the 10 µF capacitor, and finally the 2-Ω resistor to V_DDC. These traces
should be kept short.
2Ω
V_DDC
10 µF
V_DDPLL
0.1 µF 0.01 µF
Figure 35. PLL Power Supply Filter Circuits
3.2.6 Power Consumption
You can reduce power consumption in your design by controlling the power consumption of the following regions of the device:
• Extended core. Use the SC1400 Stop and Wait modes by issuing a stop or wait instruction.
• Clock synthesis module. Disable the PLL, timer, watchdog, or DDR clocks or disable the CLKO pin.
• AHB subsystem. Freeze or shut down the AHB subsystem using the GPSCTL[XBR_HRQ] bit.
• Peripheral subsystem. Halt the individual on-device peripherals such as the DDR memory controller, Ethernet MAC,
HDI16, TDM, UART, I²C, and timer modules.
For details, see the “Clocks and Power Management” chapter of the MSC711x Reference Manual.
MSC7116 Data Sheet, Rev. 13
48
Freescale Semiconductor