MSC7116_08 Datasheet, PDF (26/60 Pages) Freescale Semiconductor, Inc – Low-Cost 16-bit DSP with DDR Controller and 10/100 Mbps Ethernet MAC

Electrical Characteristics
2.5.4 DDR DRAM Controller Timing
This section provides the AC electrical characteristics for the DDR DRAM interface.
2.5.4.1 DDR DRAM Input AC Timing Specifications
Table 17 provides the input AC timing specifications for the DDR DRAM interface.
Table 17. DDR DRAM Input AC Timing
No.
Parameter
Symbol
Min
Max
Unit
— AC input low voltage
— AC input high voltage
201 Maximum Dn input setup skew relative to DQSn input
V_IL
—
V_REF – 0.31
V
V_IH
V_REF + 0.31
V_DDM + 0.3
V
—
—
900
ps
202 Maximum Dn input hold skew relative to DQSn input
—
—
900
ps
Notes: 1. Maximum possible skew between a data strobe (DQSn) and any corresponding bit of data (D[8n + {0...7}] if 0 ≤ n ≤ 7).
2. See Table 18 for t_CK value.
3. Dn should be driven at the same time as DQSn. This is necessary because the DQSn centering on the DQn data tenure is
done internally.
DQSn
Dn
202
202
D0
D1
201
Note: DQS centering is done internally. ²⁰¹
Figure 5. DDR DRAM Input Timing Diagram
2.5.4.2 DDR DRAM Output AC Timing Specifications
Table 18 and Table 19 list the output AC timing specifications and measurement conditions for the DDR DRAM
interface.
Table 18. DDR DRAM Output AC Timing
No.
Parameter
200 CK cycle time, (CK/CK crossing)¹
• 100 MHz (DDR200)
• 150 MHz (DDR300)
204 An/RAS/CAS/WE/CKE output setup with respect to CK
205 An/RAS/CAS/WE/CKE output hold with respect to CK
206 CSn output setup with respect to CK
207 CSn output hold with respect to CK
208 CK to DQSn²
Symbol
t_CK
t_DDKHAS
t_DDKHAX
t_DDKHCS
t_DDKHCX
t_DDKHMH
Min
10
6.67
0.5 × t_CK – 1000
0.5 × t_CK – 1000
0.5 × t_CK – 1000
0.5 × t_CK – 1000
–600
Max
—
—
—
—
—
—
600
Unit
ns
ns
ps
ps
ps
ps
ps
MSC7116 Data Sheet, Rev. 13
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Freescale Semiconductor