MSC7116_08 Datasheet, PDF (21/60 Pages) Freescale Semiconductor, Inc – Low-Cost 16-bit DSP with DDR Controller and 10/100 Mbps Ethernet MAC

Electrical Characteristics
2.5 AC Timings
This section presents timing diagrams and specifications for individual signals and parallel I/O outputs and inputs. All AC
timings are based on a 30 pF load, except where noted otherwise, and a 50 Ω transmission line. For any additional pF, use the
following equations to compute the delay:
— Standard interface: 2.45 + (0.054 × C_load) ns
— DDR interface: 1.6 + (0.002 × C_load) ns
2.5.1 Clock and Timing Signals
The following tables describe clock signal characteristics. Table 6 shows the maximum frequency values for internal (core,
reference, and peripherals) and external (CLKO) clocks. You must ensure that maximum frequency values are not exceeded (see
Section 2.5.2 for the allowable ranges when using the PLL).
Characteristic
Core clock frequency (CLOCK)
External output clock frequency (CLKO)
Memory clock frequency (CK, CK)
TDM clock frequency (TxRCK, TxTCK)
Table 6. Maximum Frequencies
Maximum in MHz
266
67
133
50
Table 7. Clock Frequencies in MHz
Characteristic
Symbol
Min
CLKIN frequency
F_CLKIN
10
CLOCK frequency
F_CORE
—
CK, CK frequency
F_CK
—
TDMxRCK, TDMxTCK frequency
F_TDMCK
—
CLKO frequency
F_CKO
—
AHB/IPBus/APB clock frequency
F_BCK
—
Note: The rise and fall time of external clocks should be 5 ns maximum
Max
100
266
133
50
67
133
Table 8. System Clock Parameters
Characteristic
Min
CLKIN frequency
10
CLKIN slope
—
CLKIN frequency jitter (peak-to-peak)
—
CLKO frequency jitter (peak-to-peak)
—
Max
100
5
1000
133
Unit
MHz
ns
ps
ps
MSC7116 Data Sheet, Rev. 13
Freescale Semiconductor
21