MSC7116_08 Datasheet, PDF (38/60 Pages) Freescale Semiconductor, Inc – Low-Cost 16-bit DSP with DDR Controller and 10/100 Mbps Ethernet MAC

2.5.11 Event Timing
Table 29. EVNT Signal Timing
Number
Characteristics
Type
Min
67
68
Notes: 1.
2.
3.
EVNT as input
Asynchronous
1.5 × APBCLK periods
EVNT as output
Synchronous to core clock
1 APBCLK period
Refer to Table 27 for a definition of the APBCLK period.
Direction of the EVNT signal is configured through the GPIO and Event port registers.
Refer to the signal chapter in the MSC711x Reference Manual for details on EVNT pin functionality.
Figure 24 shows the signal behavior of the EVNT pins.
EVNT in
EVNT out
67
68
Figure 24. EVNT Pin Timing
2.5.12 GPIO Timing
Table 30. GPIO Signal Timing^1,2,3
Number
Characteristics
Type
Min
601
GPI^4.5
602
GPO⁵
Asynchronous
Synchronous to core clock
1.5 × APBCLK periods
1 APBCLK period
603
Port A edge-sensitive interrupt
604
Port A level-sensitive interrupt
Asynchronous
Asynchronous
1.5 × APBCLK periods
3 × APBCLK periods⁶
Notes: 1. Refer to Table 27 for a definition of the APBCLK period.
2. Direction of the GPIO signal is configured through the GPIO port registers.
3. Refer to Section 1.5 for details on GPIO pin functionality.
4. GPI data is synchronized to the APBCLK internally and the minimum listed is the capability of the hardware to capture data
into a register when the GPADR is read. The specification is not tested due to the asynchronous nature of the input and
dependence on the state of the DSP core. It is guaranteed by design.
5. The output signals cannot toggle faster than 75 MHz.
6. Level-sensitive interrupts should be held low until the system determines (via the service routine) that the interrupt is
acknowledged.
Figure 25 shows the signal behavior of the GPI/GPO pins.
601
GPI
602
GPO
Figure 25. GPI/GPO Pin Timing
MSC7116 Data Sheet, Rev. 13
38
Freescale Semiconductor