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MSC7116_08 Datasheet, PDF (56/60 Pages) Freescale Semiconductor, Inc – Low-Cost 16-bit DSP with DDR Controller and 10/100 Mbps Ethernet MAC | |||
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Hardware Design Considerations
3.5.3 General Routing
The general routing considerations for the DDR are as follows:
⢠All DDR signals must be routed next to a solid reference:
â For data, next to solid ground planes.
â For address/command, power planes if necessary.
⢠All DDR signals must be impedance controlled. This is system dependent, but typical values are 50â60 ohm.
⢠Minimize other cross-talk opportunities. As possible, maintain at least a four times the trace width spacing between all
DDR signals to non-DDR signals.
⢠Keep the number of vias to a minimum to eliminate additional stubs and capacitance.
⢠Signal group routing priorities are as follows:
â DDR clocks.
â Route MVTT/MVREF.
â Data group.
â Command/address.
⢠Minimize data bit jitter by trace matching.
3.5.4 Routing Clock Distribution
The DDR clock distribution considerations are as follows:
⢠DDR controller supports six clock pairs:
â 2 DIMM modules.
â Up to 36 discrete chips.
⢠For route traces as for any other differential signals:
â Maintain proper difference pair spacing.
â Match pair traces within 25 mm.
⢠Match all clock traces to within 100 mm.
⢠Keep all clocks equally loaded in the system.
⢠Route clocks on inner critical layers.
3.5.5 Data Routing
The DDR data routing considerations are as follows:
⢠Route each data group (8-bits data + DQS + DM) on the same layer. Avoid switching layers within a byte group.
⢠Take care to match trace lengths, which is extremely important.
⢠To make trace matching easier, let adjacent groups be routed on alternate critical layers.
⢠Pin swap bits within a byte group to facilitate routing (discrete case).
⢠Tight trace matching is recommended within the DDR data group. Keep each 8-bit datum and its DM signal within ±
25 mm of its respective strobe.
⢠Minimize lengths across the entire DDR channel:
â Between all groups maintain a delta of no more than 500 mm.
â Allows greater flexibility in the design for readjustments as needed.
⢠DDR data group separation:
â If stack-up allows, keep DDR data groups away from the address and control nets.
â Route address and control on separate critical layers.
â If resistor networks (RNs) are used, attempt to keep data and command lines in separate packages.
MSC7116 Data Sheet, Rev. 13
56
Freescale Semiconductor
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