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XPC8260ZUIFBC Datasheet, PDF (5/50 Pages) Freescale Semiconductor, Inc – PowerQUICC II Integrated Communications Processor Hardware Specifications | |||
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Features
â Transparent
â UART (low-speed operation)
â One serial peripheral interface identical to the MPC860 SPI
â One inter-integrated circuit (I2C) controller (identical to the MPC860 I2C controller)
â Microwire compatible
â Multiple-master, single-master, and slave modes
â Up to eight TDM interfaces (four on the MPC8255)
â Supports two groups of four TDM channels for a total of eight TDMs
â 2,048 bytes of SI RAM
â Bit or byte resolution
â Independent transmit and receive routing, frame synchronization
â Supports T1, CEPT, T1/E1, T3/E3, pulse code modulation highway, ISDN basic rate, ISDN
primary rate, Freescale interchip digital link (IDL), general circuit interface (GCI), and
user-defined TDM serial interfaces
â Eight independent baud rate generators and 20 input clock pins for supplying clocks to FCCs,
SCCs, SMCs, and serial channels
â Four independent 16-bit timers that can be interconnected as two 32-bit timers
Additional features of the MPC826xA family are as follows:
⢠CPM
â 32-Kbyte dual-port RAM
â Additional MCC host commands
â Eight transfer transmission convergence (TC) layers between the TDMs and FCC2 to support
inverse multiplexing for ATM capabilities (IMA) (MPC8264 and MPC8266 only)
⢠CPM multiplexing
â FCC2 can also be connected to the TC layer.
⢠TC layer (MPC8264 and MPC8266 only)
â Each of the 8 TDM channels is routed in hardware to a TC layer block
â Protocol-specific overhead bits may be discarded or routed to other controllers by the SI
â Performing ATM TC layer functions (according to ITU-T I.432)
â Transmit (Tx) updates
- Cell HEC generation
- Payload scrambling using self synchronizing scrambler (programmable by the user)
- Coset generation (programmable by the user)
- Cell rate by inserting idle/unassigned cells
â Receive (Rx) updates
- Cell delineation using bit by bit HEC checking and programmable ALPHA and DELTA
parameters for the delineation state machine
- Payload descrambling using self synchronizing scrambler (programmable by the user)
MPC8260A PowerQUICC⢠II Integrated Communications Processor Hardware Specifications, Rev. 2.0
Freescale Semiconductor
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