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XPC8260ZUIFBC Datasheet, PDF (3/50 Pages) Freescale Semiconductor, Inc – PowerQUICC II Integrated Communications Processor Hardware Specifications | |||
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Features
â PowerPC architecture-compliant memory management unit (MMU)
â Common on-chip processor (COP) test interface
â High-performance (6.6â7.65 SPEC95 benchmark at 300 MHz; 1.68 MIPs/MHz without
inlining and 1.90 Dhrystones MIPS/MHz with
â Supports bus snooping for data cache coherency
â Floating-point unit (FPU)
⢠Separate power supply for internal logic and for I/O
⢠Separate PLLs for G2 core and for the CPM
â G2 core and CPM can run at different frequencies for power/performance optimization
â Internal core/bus clock multiplier that provides 1.5:1, 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios
â Internal CPM/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios
⢠64-bit data and 32-bit address 60x bus
â Bus supports multiple master designs
â Supports single- and four-beat burst transfers
â 64-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller
â Supports data parity or ECC and address parity
⢠32-bit data and 18-bit address local bus
â Single-master bus, supports external slaves
â Eight-beat burst transfers
â 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller
⢠60x-to-PCI bridge (MPC8265 and MPC8266 only)
â Programmable host bridge and agent
â 32-bit data bus, 66 MHz, 3.3 V
â Synchronous and asynchronous 60x and PCI clock modes
â All internal address space available to external PCI host
â DMA for memory block transfers
â PCI-to-60x address remapping
⢠System interface unit (SIU)
â Clock synthesizer
â Reset controller
â Real-time clock (RTC) register
â Periodic interrupt timer
â Hardware bus monitor and software watchdog timer
â IEEE Std. 1149.1⢠standard JTAG test access port
⢠Twelve-bank memory controller
â Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash and other user-
definable peripherals
â Byte write enables and selectable parity generation
MPC8260A PowerQUICC⢠II Integrated Communications Processor Hardware Specifications, Rev. 2.0
Freescale Semiconductor
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