XPC8260ZUIFBC Datasheet, PDF (16/50 Pages) Freescale Semiconductor, Inc – PowerQUICC II Integrated Communications Processor Hardware Specifications

Electrical and Thermal Characteristics
Figure 4 shows the FCC internal clock.
BRG_OUT
sp16a
FCC input signals
sp17a
FCC output signals
Note: When GFMR[TCI] = 0
sp36a/sp37a
FCC output signals
Note: When GFMR[TCI] = 1
Figure 4. FCC Internal Clock Diagram
Figure 5 shows the SCC/SMC/SPI/I²C external clock.
sp36a/sp37a
Serial CLKin
SCC/SMC/SPI/I2C input signals
(See note.)
SCC/SMC/SPI/I2C output signals
(See note.)
sp18b
sp19b
sp38b/sp39b
Note: There are four possible timing conditions for SCC and SPI:
1. Input sampled on the rising edge and output driven on the rising edge (shown).
2. Input sampled on the rising edge and output driven on the falling edge.
3. Input sampled on the falling edge and output driven on the falling edge.
4. Input sampled on the falling edge and output driven on the rising edge.
Figure 5. SCC/SMC/SPI/I²C External Clock Diagram
MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 2.0
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Freescale Semiconductor