XPC8260ZUIFBC Datasheet, PDF (2/50 Pages) Freescale Semiconductor, Inc – PowerQUICC II Integrated Communications Processor Hardware Specifications

Features
Figure 1 shows the block diagram for the MPC8266, the HiP4 superset device. Shaded portions indicate
functionality that is not available on all devices; refer to the notes.
G2 Core
16 Kbytes
I-Cache
I-MMU
16 Kbytes
D-Cache
D-MMU
Communication Processor Module (CPM)
Timers
Parallel I/O
Baud Rate
Generators
Interrupt
Controller
32 Kbytes
Dual-Port RAM
32-bit RISC Microcontroller
and Program ROM
IMA^1,3
Microcode
Serial
DMAs
4 Virtual
IDMAs
System Interface Unit
(SIU)
Bus Interface Unit
60x-to-PCI
Bridge^2,3
60x-to-Local
Bridge
Memory Controller
Clock Counter
System Functions
60x Bus
PCI Bus^2,3
32 bits, up to 66 MHz
or
Local Bus
32 bits, up to 83 MHz
4
4
MCC1 MCC2 FCC1 FCC2 FCC3 SCC1 SCC2 SCC3 SCC4 SMC1 SMC2 SPI
I²C
TC Layer Hardware^1,3
Time Slot Assigner
Serial Interface
8 TDM Ports⁵
3 MII
Ports⁶
2 UTOPIA
Ports
Non-Multiplexed
I/O
Notes:
1 _MPC8264
2 _MPC8265
3 _MPC8266
4 _{Not on MPC8255}
5 _{4 TDM ports on the MPC8255}
6 _{2 MII ports on the MPC8255}
Figure 1. MPC8266 Block Diagram
1 Features
The major features of the MPC826xA family are as follows:
• Dual-issue integer core
— A core version of the EC603e microprocessor
— System core microprocessor supporting frequencies of 150–300 MHz
— Separate 16-Kbyte data and instruction caches:
– Four-way set associative
– Physically addressed
– LRU replacement algorithm
MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 2.0
2
Freescale Semiconductor