XPC8260ZUIFBC Datasheet, PDF (20/50 Pages) Freescale Semiconductor, Inc – PowerQUICC II Integrated Communications Processor Hardware Specifications

Electrical and Thermal Characteristics
Figure 9 shows the interaction of several bus signals.
CLKin
AACK/ARTRY/TA/TS/TEA/
DBG/BG/BR input signals
sp11
sp12
sp10
sp10
DATA bus normal mode
input signal
sp15
sp10
All other input signals
PSDVAL/TEA/TA output signals
ADD/ADD_atr/BADDR/CI/
GBL/WT output signals
sp31
sp32
sp33a
sp30
sp30
sp30
DATA bus output signals
sp35
sp30
All other output signals
Figure 9. Bus Signals
Figure 10 shows signal behavior for all parity modes (including ECC, RMW parity, and standard parity).
CLKin
DATA bus, ECC, and PARITY mode input signals
sp13
sp10
DP mode input signal
sp14
DP mode output signal
Figure 10. Parity Mode Diagram
sp10
sp33b/sp30
MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 2.0
20
Freescale Semiconductor