XPC8260ZUIFBC Datasheet, PDF (17/50 Pages) Freescale Semiconductor, Inc – PowerQUICC II Integrated Communications Processor Hardware Specifications

Figure 6 shows the SCC/SMC/SPI/I²C internal clock.
Electrical and Thermal Characteristics
BRG_OUT
SCC/SMC/SPI/I2C input signals
(See note.)
sp18a
sp19a
sp38a/sp39a
SCC/SMC/SPI/I2C output signals
(See note.)
Note: There are four possible timing conditions for SCC and SPI:
1. Input sampled on the rising edge and output driven on the rising edge (shown).
2. Input sampled on the rising edge and output driven on the falling edge.
3. Input sampled on the falling edge and output driven on the falling edge.
4. Input sampled on the falling edge and output driven on the rising edge.
Figure 6. SCC/SMC/SPI/I²C Internal Clock Diagram
Figure 7 shows TDM input and output signals.
Serial CLKin
TDM input signals
TDM output signals
sp20
sp21
sp40/sp41
Note: There are four possible TDM timing conditions:
1. Input sampled on the rising edge and output driven on the rising edge (shown).
2. Input sampled on the rising edge and output driven on the falling edge.
3. Input sampled on the falling edge and output driven on the falling edge.
4. Input sampled on the falling edge and output driven on the rising edge.
Figure 7. TDM Signal Diagram
MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 2.0
Freescale Semiconductor
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