XPC8260ZUIFBC Datasheet, PDF (49/50 Pages) Freescale Semiconductor, Inc – PowerQUICC II Integrated Communications Processor Hardware Specifications

Document Revision History
Table 23. Document Revision History (continued)
Revision Date
Substantive Changes
0.9
8/2003 • Note: In revision 0.3, sp30 (Table 10) was changed. This change was not previously recorded in this
“Document Revision History” Table.
• Removal of “HiP4 PowerQUICC II Documentation” table. These supplemental specifications have
been replaced by revision 1 of the MPC8260 PowerQUICC II™ Family Reference Manual.
• Figure 1 and Section 1, “Features”: Addition of MPC8255 notes
• Addition of Figure 2
• Addition of VCCSYN to “Note: Core, PLL, and I/O Supply Voltages” following Table 2
• Addition of note 1 to Table 3
• Table 4: Changes to θ_JA and θ_JB and θ_JC.
• Addition of notes or modifications to Figure 6, Figure 7, and Figure 8
• Table 9: Change of sp10.
• Addition of Table 15.
• Addition of note 2 to Table 21
• Table 21: Addition of FCC2 Rx and Tx [3,4] to CPM pins PD7, PD18, PD19, and PD29. Also, the
addition of SPICLK to PC19. They are documented correctly in the parallel I/O ports chapter in the
MPC8260 PowerQUICC II™ Family Reference Manual but had previously been omitted from
Table 21.
0.8
1/2003 • Table 2: Modification to supply voltage ranges reflected in notes 2, 3, and 4.
• Table 4: Addition of θ_JB and θ_JC.
• Table 7, Figure 8: Addition of sp42a/sp43a.
• Figure 3, Figure 4: Addition of note for FCC output.
• Figure 5, Figure 6, Figure 7: Addition of notes.
• Table 14, Table 17, and Table 19: Removal of PLL bypass mode from clock tables.
0.7
5/2002 • Section 1, “Features”: minimum supported core frequency of 150 MHz
• Section 1, “Features”: updated performance values (under “Dual-issue integer core”)
• Table 2: Note 2 (changes in italics): “...less than or equal to 233 MHz, 166 MHz CPM...”
• Table 2: Addition of note 3.
0.6
3/2002 • Table 21: Modified notes to pins AE11 and AF25.
0.5
3/2002 • Table 21: Modified notes to pins AE11 and AF25.
• Table 21: Addition of note to pins AA1 and AG4 (Therm0 and Therm1).
0.4
2/2002 • Note 2 for Table 2 (changes in italics): “...greater than or equal to 266 MHz, 200 MHz CPM...”
• Table 19: Core and bus frequency values for the following ranges of MODCK_HMODCK: 0011_000
to 0011_100 and 1011_000 to 1011_1000
• Table 21: Notes added to pins at AE11, AF25, U5, and V4.
0.3
11/2001 • Table 1: note 3
• Section 2.1: Removal of “Warning” recommending use of bootstrap diodes. They are not needed.
• Table 9: Change to sp12.
• Table 10: Change to sp32.
• Note 2 for Table 16 and Table 17
• Addition of note at beginning of Section 3.2
• Note 1 for Table 18 and Table 19
• Table 21: Additions to B27, C28, D25, D27, E26, G29, H26–28, N25, P29, AF25, AA25, AB27
0.2
11/2001 • Revision of Table 5, “Power Dissipation”
• Modifications to Figure 9, Table 2,Table 10, Table 11, and Table 18
• Modification to pinout diagram, Figure 13
• Additional revisions to text and figures throughout
0.1
8/2001 • Table 8: Change to sp20/sp21.
0
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Initial version
MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 2.0
Freescale Semiconductor
49