33888 Datasheet, PDF (35/40 Pages) Freescale Semiconductor, Inc – Quad High-Side and Octal Low-Side Switch for Automotive

ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 2.0)
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 2.0)
33888PNB
Introduction
This thermal addendum is provided as a supplement to the MC33888 technical
datasheet. The addendum provides thermal performance information that may be
critical in the design and development of system applications. All electrical,
application, and packaging information is provided in the datasheet.
Packaging and Thermal Considerations
This package is a dual die package. There are two heat sources in the package
independently heating with P₁ and P₂. This results in two junction temperatures,
T_J1 and T_J2, and a thermal resistance matrix with Rθ_JAmn.
For m, n = 1, Rθ_JA11 is the thermal resistance from Junction 1 to the reference
temperature while only heat source 1 is heating with P₁.
For m = 1, n = 2, Rθ_JA12 is the thermal resistance from Junction 1 to the
reference temperature while heat source 2 is heating with P₂. This applies to Rθ_J21
and Rθ_J22, respectively.
T_J1
T_J2
=
R_θJA11
R_θJA21
R_θJA12
R_θJA22
.
P₁
P₂
36-PIN PQFN
PNB SUFFIX
98ARL10544D
36-PIN PQFN
14 mm x 14 mm
Note For package dimensions, refer to
the 33888 device data sheet.
The stated values are solely for a thermal performance comparison of one package to another in a standardized environment.
This methodology is not meant to and will not predict the performance of a package in an application-specific environment. Stated
values were obtained by measurement and simulation according to the standards listed below.
Standards
Table 16. Thermal Performance Comparison
Thermal
Resistance
1 = Power Chip, 2 = Logic Chip [°C/W]
m = 1,
n=1
m = 1, n = 2
m = 2, n = 1
m = 2,
n=2
Ρ_θJAmn ^{(1), (2)}
19
18
20
Ρ_θJAmn ^{(1), (2)}
6.0
5.0
6.0
Ρ_θJAmn ^{(1), (2)}
37
36
37
Ρ_θJAmn ^{(1), (2)}
<1
0
1
Notes
1. Per JEDEC JESD51-2 at natural convection, still air
condition.
2. 2s2p thermal test board per JEDEC JESD51-7and
JESD51-5.
3. Per JEDEC JESD51-8, with the board temperature on the
center trace near the power outputs.
4. Single layer thermal test board per JEDEC JESD51-3 and
JESD51-5.
5. Thermal resistance between the die junction and the
exposed pad, “infinite” heat sink attached to exposed pad.
1.0
0.2
1.0
0.2
* All measurements
are in millimeters
Note: Recommended via diameter is 0.5 mm. PTH (plated through
hole) via must be plugged / filled with epoxy or solder mask in order
to minimize void formation and to avoid any solder wicking into the
via.
Figure 14. Surface Mount for Power PQFN
with Exposed Pads
Analog Integrated Circuit Device Data
Freescale Semiconductor
33888
35