33888 Datasheet, PDF (16/40 Pages) Freescale Semiconductor, Inc – Quad High-Side and Octal Low-Side Switch for Automotive

ELECTRICAL CONNECTIONS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 6. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 6.0 V ≤ V_PWR ≤ 27 V, 4.5 V ≤ V_DD ≤ 5.5 V, -40°C ≤ T_J ≤ 150°C unless otherwise noted.
Typical values noted reflect the approximate parameter means at T_A = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUT TIMING (continued)
Watchdog Timeout ⁽³⁵⁾
Peak Current Limit Timer ⁽³⁶⁾
Direct Input Switching Frequency ⁽³⁷⁾
SPI INTERFACE TIMING ⁽³⁸⁾
Recommended Frequency of SPI Operation
Normal Mode
Extended Mode: V_DD = 3.4 V; V_PWR = 4.5 V, APNB Suffix Only
Required Low State Duration for RST ⁽³⁹⁾
Rising Edge of CS to Falling Edge of CS (Required Setup Time) ⁽⁴⁰⁾
Rising Edge of RST to Falling Edge of CS (Required Setup Time) ⁽⁴⁰⁾
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time) ⁽⁴⁰⁾
Required High State Duration of SCLK (Required Setup Time) ⁽⁴⁰⁾
Required Low State Duration of SCLK (Required Setup Time) ⁽⁴⁰⁾
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time) ⁽⁴⁰⁾
SI to Falling Edge of SCLK (Required Setup Time) ⁽⁴⁰⁾
Falling Edge of SCLK to SI (Required Hold Time) ⁽⁴⁰⁾
SO Rise Time
C_L = 200 pF
SO Fall Time
C_L = 200 pF
SI, CS, SCLK, Incoming Signal Rise Time ⁽⁴¹⁾
SI, CS, SCLK, Incoming Signal Fall Time ⁽⁴¹⁾
Time from Falling Edge of CS to SO Low Impedance ⁽⁴²⁾
Time from Rising Edge of CS to SO High Impedance ⁽⁴³⁾
Time from Rising Edge of SCLK to SO Data Valid ⁽⁴⁴⁾
0.2 V_DD ≤ SO ≥ 0.8 V_DD, C_L = 200 pF
t _WDTO
340
584
770
ms
t _PCT
40
70
100
ms
f _PWM
–
125
–
Hz
f _SPI
–
–
t _WRST
–
t _CS
–
t _ENBL
–
t _LEAD
–
t _WSCLKh
–
t _WSCLKl
–
t _LAG
–
t _{SI (SU)}
–
t _{SI (HOLD)}
–
t _RSO
–
t _FSO
–
t _RSI
–
t _FSI
–
t _SO(EN)
–
t _SO(DIS)
–
t _VALID
–
MHz
–
3.0
–
2.1
50
167
ns
–
300
ns
–
5.0
µs
50
167
ns
–
167
ns
–
167
ns
50
167
ns
25
83
ns
25
83
ns
ns
25
50
ns
25
50
–
50
ns
–
50
ns
–
145
ns
65
145
ns
ns
65
105
Notes
35. Watchdog timeout delay is measured from the rising edge of WAKE or RST from the sleep state to the HS[0:1] turn-ON with the outputs
driven OFF and the FSI floating. The accuracy of t _WDTO is maintained for all configured watchdog time-outs.
36. t_PCT measured from the rising edge of CS to 90% of I_LIMPKHS[x,x] when the peak current limit is enabled.
37. This frequency is a typical value. Maximum switching frequencies are dictated by the turn-ON delay, turn-OFF delay, output rise and fall
times, and the maximum allowable junction temperature.
38. Symmetrical 50% duty cycle SCLK clock period of 333 ns.
39. RST low duration measured with outputs enabled and going to OFF or disabled condition.
40. Maximum setup time required for the 33888 is the minimum guaranteed time needed from the MCU.
41. Rise and fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
42. Time required for output status data to be available for use at SO. 1.0 kΩ pullup on CS.
43. Time required for output status data to be terminated at SO. 1.0 kΩ pullup on CS.
44. Time required to obtain valid data out from SO following the rise of SCLK.
33888
16
Analog Integrated Circuit Device Data
Freescale Semiconductor