33888 Datasheet, PDF (22/40 Pages) Freescale Semiconductor, Inc – Quad High-Side and Octal Low-Side Switch for Automotive

FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
retried output will latch off after the fault timer expires and the
fault bit will remain set in the status register.
For the low-side output of interest, if a D11 : D4 bit was set
to a logic [0] in the OLCR register, the output experiencing an
overcurrent condition is not disabled until an overtemperature
fault threshold has been reached. The specific output goes
into an analog current limit mode of operation, I_LIM. The
33888 uses overtemperature shutdown to protect all outputs
in this mode of operation. If the overcurrent condition is
removed before the output has reached its overtemperature
limit, the output will function as if no fault has occurred.
Note that each pair of low-side drivers, LS4 : LS5,
LS6 : LS7, LS8 : LS9, and LS10 : LS11, consists of a 500 mA
and a 800 mA output. Each pair of outputs shares ground
bond wires. The bond wires are not rated to handle both
outputs in current limit mode simultaneously.
OVERCURRENT FAULT REQUIREMENTS: HIGH-
SIDE OUTPUT
For the high-side output of interest, the output current is
limited to one of four levels depending on the type of high-
side output, the amount of time that has elapsed since the
output was switched on, and the state of the CLOCCR
register. Assuming that bits D3 : D0 of the CLOCCR register
are at logic [0], the current limit levels of the outputs will be
initially at their peak levels as specified by the I_{LIM(PK)HS[0:3]}.
After the high-side output is switched on, the peak current
timer starts. After a period of time t _PCT, the current limit level
changes to the sustain levels I_{LIMSUSHS[x,x]}.
For the high-side output of interest, if a D3 : D0 bit of the
CLOCCR is at logic [1], then the assigned output will only
current limit at the sustain level specified by I_{LIMSUSHS[x,x]}.
Current is limited until the overtemperature circuitry shuts
OFF the device. The device turns ON automatically when the
temperature fails below the T_LIM(HYS). This cycle continues
indefinitely until action is taken by the master to shut the
output(s) OFF.
LOGIC COMMANDS AND REGISTERS
SPI INTERFACE AND PROTOCOL DESCRIPTION
The SPI interface has full duplex, three-wire synchronous
data transfer and has four I/O lines associated with it: Serial
Clock (SCLK), Serial Input (SI), Serial Output (SO), and Chip
Select (CS).
The SI/SO pins of the 33888 follow a first-in first-out (D15 /
D0) protocol with both input and output words transferring the
most significant bit first. All inputs are compatible with 5.0 V
CMOS logic levels. During SPI output control, a logic [0] in a
message word will result in the designated output being
turned off. Similarly, a logic [1] will turn on a corresponding
output.
The SPI lines perform the following functions:
Serial Clock (SCLK)
The SCLK pin clocks the internal shift registers of the
33888. The serial input (SI) pin accepts data into the input
shift register on the falling edge of the SCLK signal while the
serial output pin (SO) shifts data information out of the SO
line driver on the rising edge of the SCLK signal. It is
important that the SCLK pin be in a logic [0] state whenever
the chip select (CS) makes any transition. For this reason, it
is recommended that the SCLK pin be kept in a logic [0] state
as long as the device is not accessed (CS in logic [1] state).
SCLK has an active internal pulldown, I_DWN. When CS is
logic [1], signals at the SCLK and SI pins are ignored and SO
is tri-stated (high impedance). (See Figures 8 and 9 on
page 23.)
Serial Interface (SI)
This is a serial interface (SI) command data input pin.
Each SI bit is read on the falling edge of SCLK. A 16-bit
stream of serial data is required on the SI pin, starting with
D15 to D0. The 12 outputs of the 33888 are configured and
controlled using the 3-bit addressing scheme and the
12 assigned data bits designed into the 33888. SI has an
active internal pulldown, I_DWN.
Serial Output (SO)
The SO data pin is a tri-stateable output from the shift
register. The SO pin remains in a high-impedance state until
the CS pin is put into a logic [0] state. The SO data report the
status of the outputs as well as provide the capability to
reflect the state of the direct inputs. The SO pin changes
states on the rising edge of SCLK and reads out on the falling
edge of SCLK. When an output is ON or OFF and not faulted,
the corresponding SO bit, OD11: OD0, is a logic [0]. If the
output is faulted, the corresponding SO state is a logic [1]. SO
OD14 : OD12 reflect the state of six various inputs (three at a
time) depending upon the reported state of the previously
written watchdog bit OD15.
Chip Select (CS)
The CS pin enables communication with the master
microcontroller (MCU). When this pin is in a logic [0] state,
the 33888 is capable of transferring information to and
receiving information from the MCU. The 33888 latches in
data from the input shift registers to the addressed registers
on the rising edge of CS. The 33888 transfers status
information from the power outputs to the shift registers on
the falling edge of CS. The output driver on the SO pin is
enabled when CS is logic [0]. CS is only transitioned from a
logic [1] state to a logic [0] state when SCLK is a logic [0]. CS
has an active internal pullup, I_UP.
The 33888 is capable of communicating directly with the
MCU via the 16-bit SPI protocol as described in the next
section.
33888
22
Analog Integrated Circuit Device Data
Freescale Semiconductor