33888 Datasheet, PDF (20/40 Pages) Freescale Semiconductor, Inc – Quad High-Side and Octal Low-Side Switch for Automotive

FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
WATCHDOG AND FAIL-SAFE OPERATION
The watchdog is enabled and a timeout is started when the
WAKE or RST transitions from logic [0] to logic [1]. The
WAKE input is capable of being pulled up to V_PWR with a
series limiting resistance that limits the internal clamp current.
The timeout is a multiple of an internal oscillator. As long as
the WDIN pin or the WD bit (D15) of an incoming SPI
message is toggled within the minimum watchdog timeout,
WDTO (or a divided value configured during a WDCSCR
message), then the device will operate normally. If the
watchdog timeout occurs before the WD bit or the WDIN pin
is toggled, then the device will revert to a Fail-Safe mode until
the device is re initialized (if the FSI pin is left disconnected).
During Fail-Safe mode, all outputs will be OFF except for
HS0 and HS2, which will be driven ON regardless of the state
of the various direct inputs and modes (Table 7). The device
can be brought out of the Fail-Safe mode by transitioning the
WAKE and RST pins from logic [1] to logic [0]. In the event
the WAKE pin was not transitioned to a logic [1] during
normal operation and the watchdog times out, then the
device can be brought out of fail-safe by bringing the RST to
a logic [0]. If the FSI pin is tied to GND, then the watchdog,
and therefore fail-safe operation, will be disabled.
DEFAULT MODE
The default mode describes the state of the device after
first applying V_PWR voltage or a reset transition from logic [0]
to logic [1] prior to SPI communication. In the default mode,
all outputs will be off (assuming that the direct inputs ILS and
IHS[0:3] and the WAKE pin are at logic [0] ). All of the specific
pin functions will operate as though all of the addressable
configuration register bits were set to logic [0]. This means,
for example, that all of the low-side outputs will be
controllable by the ILS pin, and that all high-side outputs will
be controllable via their respective IHS pins. During the
default mode, all high-side drivers will default with open load
detection enabled. All low-side drivers will default with open
load detection disabled. This mode allows limited control of
the 33888 with the direct inputs in the absence of an SPI.
Returning the device to the default state after a period of
normal operation, followed by the removal of the V_PWR
voltage, requires that the RST input be held at a logic [0] state
until V_PWR falls to a level below 2.0 V. If the RST and V_DD
input levels are normal, then failure to allow V_PWR to fall
below 2.0 V will result in an internal bias circuit clamping the
V_PWR pin to approximately 3.5 V. Once V_PWR falls below
2.0 V, the RST can be returned to 5.0 V without re-enabling
the bias circuit.
Table 7. Fail-Safe Operation and Transitions to Other
33888 Modes
WAKE
RS
T
WDTO
HS0
HS2
LS[4:11],
HS[1,3]
Comments
0 0 x OF OF OFF ^{Device in Sleep mode.}
FF
1 0 NO OF OF OFF ^{All outputs are OFF.}
FF
When RST transitions to
logic [1], device is in
default.
1 0 YES ON ON OFF Fail-Safe mode. Device
reset into Default mode
by transitioning WAKE
to logic [0].
0 1 NO S S
S
Device in Normal
operating mode.
0 1 YES ON ON OFF ^{Fail-Safe mode. Device}
reset into Default mode
by transitioning RST to
logic [0].
1 1 NO S S
S
Device in Normal
operating mode.
1 1 YES ON ON OFF Fail-Safe mode. Device
reset into Default mode
by transitioning RST
and WAKE to logic [0].
Assumptions: Normal operating voltage and junction temperatures,
FSI pin floating.
x = Don’t care.
S = State determined by SPI and/or direct input configurations.
FAULT LOGIC REQUIREMENTS
The 33888 indicates all of the following faults as they
occur:
• Overtemperature Fault
• Overvoltage Fault
• Open Load Fault
• Overcurrent Fault
With the exception of the overvoltage, these faults are
output specific. The overvoltage fault is a global fault. The
overcurrent fault is only reported for the low-side outputs.
The 33888 low-side outputs incorporate an internal fault
filter, t _DLY(FS). The fault timer filters noise and switching
transients for overcurrent faults when the output is ON and
open load faults when the output is OFF. All faults are latched
and indicated by a logic [1] for each output in the 33888
status word (Table 10, page 25). If the fault is removed, the
status bit for the faulted output will be cleared by a rising edge
on CS.
33888
20
Analog Integrated Circuit Device Data
Freescale Semiconductor