33888 Datasheet, PDF (25/40 Pages) Freescale Semiconductor, Inc – Quad High-Side and Octal Low-Side Switch for Automotive

FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Address 110 — Watchdog and Current Sense
Configuration Register (WDCSCR)
The WDCSCR register is used by the MCU to configure
the watchdog timeout and the CSNS0-1 and CSNS2-3 pins.
The watchdog timeout is configured using bits D4 and D5.
The state of D4 and D5 determine the divided value of the
WDTO. For example, if D5 and D4 are logic [0] and logic [0],
respectively, then the WDTO will be in the default state as
specified in Table 9, page 24. A D5 and a D4 of logic [0] and
logic [1] will result in a watchdog timeout of WDTO ÷ 2.
Similarly, a D5 and a D4 of logic [1] and logic [0] result in a
watchdog timeout of WDTO ÷ 4, and a D5 and a D4 of
logic [1] and logic [1] result in a watchdog timeout of WDTO
÷ 8. Note that when D5 and D4 bits are programmed for the
desired watchdog timeout period, the WD bit (D15) should be
toggled as well to ensure that the new timeout period is
programmed at the beginning of a new count sequence.
CSNS0 - 1 is the current sense output for the HS0 and HS1
outputs. Similarly, the CSNS2 - 3 pin is the current sense
output for the HS2 and HS3 outputs. In this mode, a logic [1]
on any or all of the message bits that control the high-side
outputs will result in the sensed current from the
corresponding output being directed out of the appropriate
CSNS output. For example, if D1 and D0 are both logic [1],
then the sensed current from HS0 and HS1 will be summed
into the CSNS0 - 1. If D2 is logic [1] and D3 is logic [0], then
only the sensed current from HS2 will be directed out of
CSNS2 - 3.
Address 001 — Open Load Configuration Register
(OLCR)
The OLCR register allows the MCU to configure each of
the outputs for open load fault detection. While in this mode,
a logic [1] on any of the D3 : D0 message bits will disable the
corresponding outputs’ circuitry that allows the device to
detect open load faults while the output is OFF. For the low-
side drivers, a logic [1] on any of the D11: D4 bits will enable
the open load detection circuitry. This feature allows the MCU
to minimize load current in some applications and may be
useful to diagnose output shorts to battery (for HS).
Address 101 — Current Limit Overcurrent Configuration
Register (CLOCCR)
The CLOCCR register allows the MCU to individually
override the peak current limit levels for each of the high-side
outputs. A logic [1] on any or all of the D3 : D0 bit(s) results in
the corresponding HS3 : HS0 output pins to current limit at the
sustain current limit level. This register also allows the MCU
to enable or disable the overcurrent shutdown of the low-side
output pins. A logic [1] on any or all of the D11: D4 message
bit(s) will result in the corresponding LS11: LS4 pins latching
off if the current exceeds I_LIM after a timeout of t _DLY(FS).
Address 011 — Not Used
Not currently used.
Address 111 — TEST
The TEST register is reserved for test and is not
accessible via SPI during normal operation.
SERIAL OUTPUT COMMUNICATION
(DEVICE STATUS RETURN DATA)
When the CS pin is pulled low, the output status register for
each output is loaded into the output register and the fault
data is clocked out MSB (OD15) first as the new message
data is clocked into the SI pin.
OD15 reflects the state of the watchdog bit (D15) that was
addressed during the prior SOCR communication (refer to
Table 10, page 25). If bit OD15 is logic [0], then the three
MSBs OD14 : OD12 will reflect the logic states of the IHS0,
IHS1, and FSI pins, respectively. If bit OD15 is logic [1], then
the same three MSB bits will reflect the logic states of the
IHS2, IHS3, and WAKE pins. The next twelve bits clocked out
of SO following a low transition of the CS pin (OD11 : OD0) will
reflect the state of each output, with a logic [1] in any of the
bits indicating that the respective output experienced a fault
condition prior to the CS transition. Any bits clocked out of the
SO pin after the first 16 will be representative of the initial
message bits that were clocked into the SI pin since the CS
pin first transitioned to a logic [0]. This feature is useful for
daisy chaining devices as well as message verification.
Following a CS transition logic [0] to logic [1], the device
determines if the message was of a valid length (a valid
message length is one that is a multiple of 16 bits) and if so,
latches the data into the appropriate registers. At this time,
the SO pin is tri-stated and the fault status register is now
able to accept new fault status information.
Table 10. Serial Output Bit Assignment
Bit SO
Sig Msg Bit
Message Bit Description
MS OD15 ^{Reflects the state of the Watchdog bit from the}
B
previously clocked-in message.
OD14 ^{If OD15 is logic [0], then this bit will reflect the state}
of the direct input IHS0. If OD15 is logic [1], then this
bit will reflect the state of IHS2.
OD13 If OD15 is logic [0], then this bit will reflect the state
of the direct input IHS1. If OD15 is logic [1], then this
bit will reflect the state of IHS3.
OD12 ^{If OD15 is logic [0], then this bit will reflect the state}
of the input FSI. If OD15 is logic [1], then this bit will
reflect the state of the input WAKE.
OD11
OD10
OD9
OD8
OD7
OD6
Reports the absence or presence of a fault on LS11.
Reports the absence or presence of a fault on LS10.
Reports the absence or presence of a fault on LS9.
Reports the absence or presence of a fault on LS8.
Reports the absence or presence of a fault on LS7.
Reports the absence or presence of a fault on LS6.
Analog Integrated Circuit Device Data
Freescale Semiconductor
33888
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