F81218 Datasheet, PDF (45/64 Pages) Feature Integration Technology Inc. – ISA/LPC to 6 UART Datasheet

Bit
Name
R/W
Description
7:0 DEC1_BASE[15:8] R/W Address high byte for ADD_DEC1/LPC_DEC1 .
F81218
6.9.3 Address Decoder Select Register 1 – index 61h
Power-on default [7:0] = 0x00h.
Bit
Name
R/W
Description
7:0 DEC1_BASE[7:0] R/W Address low byte for ADD_DEC1/LPC_DEC1.
6.9.4 Address Mask Register – index 62h
Power-on default [7:0] = 0x00h.
Bit
Name
R/W
Description
7:3 Reserved
R/W Return 0 when read.
2:0 DEC1_SEL[2:0] R/W 000 : Decode all 16 bits .
001 : Decode bit 15:1
010 : Decode bit 15:2
011 : Decode bit 15:3
100 : Decode bit 15:4
6.9.5 IRQIN1 Channel Select Register (Only for LPC) – index 70h
Power-on default [7:0] = 0x00h.
Bit
Name
R/W
Description
7:6 Reserved
R/W Return 0 when read.
5
IRQIN1_MODE R/W 0 : PCI IRQ sharing mode.
1 : ISA IRQ sharing mode.
This bit is effective in IRQ sharing mode.
4
IRQIN1_SHAR R/W 0 : IRQ is not sharing with other device.
1 : IRQ is sharing with other device.
3:0 SELIRQIN1[3:0] R/W In LPC mode , select the Serial IRQ channel.
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August, 2007
V0.33P