F81218 Datasheet, PDF (41/64 Pages) Feature Integration Technology Inc. – ISA/LPC to 6 UART Datasheet

F81218
6.6.6 UART 5 Clock Select Register – index F0h
Power-on default [7:0] = 0000_0000b.
Bit
Name
R/W
Description
7:5 Reserved
R/W Return 0 when read.
4
RS485
R/W 0: The RTS# is controlled by programming MCR[1]. (offset +4)
1: The RTS# is drive high when transmitting data and sink low when
receiving data.
3:2 Reserved
R/W Return 0 when read.
1:0 SELURCCLK1
SELURCCLK0
R/W 00 : UART 3 clock source is 1.8462MHz ( 24MHz/13 )
01/10/11 selection reserved.
6.7 UART 6 Device Control Register (LDN 5)
6.7.1 Device Enable Register – index 30h
Power-on default [7:0] = 0x01h when SOUT6/PS_238_IRQF is pull-up, else 0x00h.
Bit
Name
R/W
Description
7:1 Reserved
R/W Return 0 when read.
0
URF_EN
R/W 0 : Disable UART 6.
1 : Enable UART 6.
6.7.2 I/O Port Select Register – index 60h
Power-on default [7:0] = 0x02h when SOUT6/PS_238_IRQF is pull-up, else 0x0h.
Bit
Name
R/W
Description
7:0 URF_BASE[15:8] R/W UART 6 I/O Port Address high byte.
6.7.3 I/O Port Select Register – index 61h
Power-on default [7:0] = 0x38h when SOUT6/PS_238_IRQF is pull-up, else 0x00h.
Bit
Name
R/W
Description
7:0 URF_BASE[7:0] R/W UART 6 I/O Port Address low byte.
-36-
August, 2007
V0.33P