F81218 Datasheet, PDF (33/64 Pages) Feature Integration Technology Inc. – ISA/LPC to 6 UART Datasheet

F81218
6.2.6 IR1 Control Register – index F1h
Power-on default [7:0] = 0x44h.
Bit
Name
R/W
Description
7:5 Reserved
R/W Return 010b when read.
4:3 IRA_MODE1
IRA_MODE0
R/W 0X: Disable IR1 function.
10 : Enable IR1 function, active pulse is 1.6uS.
11 : Enable IR1 function, active pulse is 3/16 bit time.
2
Half_Full_Duplex R/W 0 : Full Duplex function for IR self test.
1 : Half Duplex function.
Return 1 when read.
1
TXINV_IRA
R/W 0 : IRTX1 is not inversed.
1 : Inverse the IRTX1.
0
RXINV_IRA
R/W 0 : IRRX1 is not inversed.
1 : Inverse the IRRX1.
6.3 UART 2 Device Control Register (LDN 1)
6.3.1 Device Enable Register – index 30h
Power-on default [7:0] = 0x01h when SOUT2/PS_2F8_IRQB or DTR2#/PS_2E0_IRQB is pull-up,
else 0x00h.
Bit
Name
R/W
Description
7:1 Reserved
R/W Return 0 when read.
0
URB_EN
R/W 0 : Disable UART 2.
1 : Enable UART 2.
6.3.2 I/O Port Select Register – index 60h
Power-on default [7:0] = 0x02h when SOUT2/PS_2F8_IRQB or DTR2#/PS_2E0_IRQB is pullup,
else 0x00h.
Bit
Name
R/W
Description
7:0 URB_BASE[15:8] R/W UART 2 I/O Port Address high byte.
-28-
August, 2007
V0.33P