F81218 Datasheet, PDF (18/64 Pages) Feature Integration Technology Inc. – ISA/LPC to 6 UART Datasheet

5.2.1.4 Divisor Latch ( MS ) – Base + 1
Power-on default [7:0] = 0x00h.
Bit
Name
R/W
Description
7:0 DLM[7:0]
R/W Baud generator divisor high byte.
Access only when LCR[7] is 1.
F81218
5.2.1.5 Interrupt Enable Register – Base + 1
Power-on default [7:0] = 0x00h.
Bit
Name
R/W
Description
7:4 Reserved
R/W Return 0 when read. Access only when LCR[7] is 0
3
EDSSI
R/W Enable Modem Status Interrupt. Access only when LCR[7] is 0.
2
ELSI
R/W Enable Line Status Error Interrupt. Access only when LCR[7] is 0.
1
ETBFI
R/W Enable Transmitter Holding Register Empty Interrupt. Access only
when LCR[7] is 0.
0
ERBFI
R/W Enable Received Data Available Interrupt. Access only when LCR[7]
is 0
5.2.1.6 Interrupt Identification Register – Base + 2
Power-on default [7:0] = 0x01h.
Bit
Name
R/W
Description
7
FIFO_EN
R
0 : FIFO is disabled
1 : FIFO is enabled.
6
FIFO_EN
R
0 : FIFO is disabled.
1 : FIFO is enabled.
5:4 Reserved
R
Return 0 when read.
3:1 IRQ_ID[2:0]
R
000 : Interrupt is caused by Modem Status
001 : Interrupt is caused by Transmitter Holding Register Empty
010 : Interrupt is caused by Received Data Available.
110 : Interrupt is caused by Character Timeout
011 : Interrupt is caused by Line Status..
0
IRQ_PENDN
R
1 : Interrupt is not pending.
0 : Interrupt is pending.
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August, 2007
V0.33P