F81218 Datasheet, PDF (35/64 Pages) Feature Integration Technology Inc. – ISA/LPC to 6 UART Datasheet

F81218
6.3.5 UART 2 Clock Select Register – index F0h
Power-on default [7:0] = 0x00h.
Bit
Name
R/W
Description
7:5 Reserved
R/W Return 0 when read.
4
RS485
R/W 0: The RTS# is controlled by programming MCR[1]. (offset +4)
1: The RTS# is drive high when transmitting data and sink low when
receiving data.
3
RXW4C_IRB
R/W 0 : No reception delay when SIR is changed from TX to RX.
1 : Reception delay 4 character-time when SIR is changed from TX
to RX.
2
TXW4C_IRB
R/W 0 : No transmission delay when SIR is changed from RX to TX.
1 : Transmission delay 4 character-time when SIR is changed from
RX to TX.
1:0 SELURACLK1 R/W 00 : UART 2 clock source is 1.8462MHz ( 24MHz/13 )
SELURACLK0
01/10/11 selection reserved.
6.3.6 IR 2 Control Register – index F1h
Power-on default [7:0] = 0x44h.
Bit
Name
R/W
Description
7:5 Reserved
R/W Return 010b when read.
4:3 IRB_MODE1
IRB_MODE0
R/W 0X: Disable IR2 function.
10 : Enable IR2 function, active pulse is 1.6uS.
11 : Enable IR2 function, active pulse is 3/16 bit time.
2
Half_Full_Duplex R/W 0 : Full Duplex function for IR self test.
1 : Half Duplex function.
Return 1 when read.
1
TXINV_IRB
R/W 0 : IRTX2 is not inversed.
1 : Inverse the IRTX2.
0
RXINV_IRB
R/W 0 : IRRX2 is not inversed.
1 : Inverse the IRRX2.
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August, 2007
V0.33P