F81218 Datasheet, PDF (31/64 Pages) Feature Integration Technology Inc. – ISA/LPC to 6 UART Datasheet

6.2 UART 1 Device Control Register (LDN 0)
F81218
6.2.1 Device Enable Register – index 30h
Power-on default [7:0] = 0x01h when SOUT1/PS_3F8_IRQA or DTR1#/PS_3E0_IRQA is pull-up,
else 0x00h.
Bit
Name
R/W
Description
7:1 Reserved
R/W Return 0 when read.
0
URA_EN
R/W 0 : Disable UART 1.
1 : Enable UART 1..
6.2.2 I/O Port Select Register – index 60h
Power-on default [7:0] = 0x03h when SOUT1/PS_3F8_IRQA or DTR1#/PS_3E0_IRQA is pullup,
else 0x00h.
Bit
Name
R/W
Description
7:0 URA_BASE[15:8] R/W UART 1 I/O Port Address high byte.
6.2.3 I/O Port Select Register – index 61h
Power-on default [7:0] = 0xF8h when SOUT1/PS_3F8_IRQA is pull-up,
0xE0h when DTR1#/PS_3E0_IRQA is pull-up, else 0x00h.
Bit
Name
R/W
Description
7:0 URA_BASE[7:0] R/W UART 1 I/O Port Address low byte.
6.2.4 IRQ Channel Select Register – index 70h
Power-on default [7:0] = 0x03h when SOUT1/PS_3F8_IRQA or DTR1#/PS_3E0_IRQA is pull-up,
else 0x00h
Bit
Name
R/W
Description
7:6 Reserved
R/W Return 0 when read.
5
URAIRQ_MODE R/W 0 : PCI IRQ sharing mode.
1 : ISA IRQ sharing mode.
This bit is effective in IRQ sharing mode.
4
URAIRQ_SHAR R/W 0 : IRQ is not sharing with other device.
1 : IRQ is sharing with other device.
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August, 2007
V0.33P