F81218 Datasheet, PDF (4/64 Pages) Feature Integration Technology Inc. – ISA/LPC to 6 UART Datasheet

F81218
6.3.5 UART 2 Clock Select Register – index F0h .......................................................................... 30
6.3.6 IR 2 Control Register – index F1h......................................................................................... 30
6.4 UART 3 Device Control Register (LDN 2) ......................................................................................... 31
6.4.1 Device Enable Register – index 30h.................................................................................. 31
6.4.2 I/O Port Select Register – index 60h.................................................................................. 31
6.4.3 I/O Port Select Register – index 61h.................................................................................. 31
6.4.4 IRQ Channel Select Register – index 70h ............................................................................. 31
6.4.5 UART 3 Clock Select Register – index F0h .......................................................................... 32
6.5 UART 4 Device Control Register (LDN 3) ......................................................................................... 32
6.5.1 Device Enable Register – index 30h.................................................................................. 32
6.5.2 I/O Port Select Register – index 60h.................................................................................. 33
6.5.3 I/O Port Select Register – index 61h.................................................................................. 33
6.5.4 IRQ Channel Select Register – index 70h ............................................................................. 33
6.5.5 UART 4 Clock Select Register – index F0h .......................................................................... 34
6.6 UART 5 Device Control Register (LDN 4) ......................................................................................... 34
6.6.1 Device Enable Register – index 30h.................................................................................. 34
6.6.2 I/O Port Select Register – index 60h.................................................................................. 34
6.6.3 I/O Port Select Register – index 61h.................................................................................. 35
6.6.5 IRQ Channel Select Register – index 70h ............................................................................. 35
6.6.6 UART 5 Clock Select Register – index F0h .......................................................................... 36
6.7 UART 6 Device Control Register (LDN 5) ......................................................................................... 36
6.7.1 Device Enable Register – index 30h.................................................................................. 36
6.7.2 I/O Port Select Register – index 60h.................................................................................. 36
6.7.3 I/O Port Select Register – index 61h.................................................................................. 36
6.7.4 IRQ Channel Select Register – index 70h ............................................................................. 37
6.7.5 UART 6 Clock Select Register – index F0h .......................................................................... 37
6.8 Address Decoder 0 Device Control Register (LDN 6) ........................................................................ 38
6.8.1 Device Enable Register – index 30h.................................................................................. 38
6.8.2 Address Decoder Select Register 0– index 60h................................................................. 38
6.8.3 Address Decoder Select Register 1– index 61h................................................................. 38
6.8.4 Address Mask Register – index 62h .................................................................................. 38
6.8.5 IRQIN0 Channel Select Register (Only for LPC) – index 70h ......................................... 39
6.9 Address Decoder 1 Device Control Register (LDN 7) ........................................................................ 39
6.9.1 Device Enable Register – index 30h.................................................................................. 39
6.9.2 Address Decoder Select Register 0 – index 60h................................................................ 39
6.9.3 Address Decoder Select Register 1 – index 61h................................................................ 40
6.9.4 Address Mask Register – index 62h .................................................................................. 40
F81218
August, 2007
V0.33P