XR16L788 Datasheet, PDF (9/42 Pages) Exar Corporation – HIGH PERFORMANCE OCTAL UART

XR16L788 OCTAL UART
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REV. 1.1.4
1.1.1 The Global Interrupt Source Registers
The XR16L788 has a global interrupt source register
set that consists of 4 consecutive registers [INT0,
INT1, INT2 and INT3]. The four registers are in the
device configuration register address space.
INT3
[0x00]
INT2
[0x00]
INT1
[0x00]
INT0
[0x00]
INT0 CHANNEL INTERRUPT INDICATOR:
INT0 Register
Individual UAR T C hannel Interrupt Status
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
Ch-7 Ch-6 Ch-5 Ch-4 Ch-3 Ch-2 Ch-1 Ch-0
All four registers default to logic zero (as indicated in
square braces) for no interrupt pending. All 8 channel
interrupts are enabled or disabled in each channel’s
IER register. INT0 shows individual status for each
channel while INT1, INT2 and INT3 show the details
of the source of each channel’s interrupt with its
unique 3-bit encoding. Figure 4 shows the 4 interrupt
registers in sequence for clarity. The 16-bit timer and
sleep wake-up interrupts are masked in the device
configuration registers, TIMERCNTL and SLEEP. An in-
terrupt is generated (if enabled) by the 788 when
awakened from sleep if all 8 channels were placed in
the sleep mode previously.
Each bit gives an indication of the channel that has
requested for service. For example, bit-0 represents
channel 0 and bit-7 indicates channel 7. Logic one in-
dicates the channel N [7:0] has called for service. The
interrupt bit clears after reading the appropriate regis-
ter of the interrupting UART channel register (ISR,
LSR and MSR). See Table 9 for interrupt clearing de-
tails.
INT1, INT2 AND INT3 INTERRUPT SOURCE LOCATOR
INT3, INT2 and INT1 provide a 24-bit (3 bits per
channel) encoded interrupt indicator. Table 3 shows
the 3 bit encoding and their priority order. The 16-bit
Timer time-out interrupt will show up only as a chan-
nel 0 interrupt. For other channels, interrupt 7 is re-
served.
.
FIGURE 4. THE GLOBAL INTERRUPT REGISTERS, INT0, INT1, INT2 AND INT3
Interrupt Registers,
INT0, INT1, INT2 and INT3
INT3 Register
INT2 Register
INT1 Register
C h a n n e l-7
Bit Bit Bit
21
0
C h a n n e l-6
Bit Bit Bit
2
1
0
C h a n n e l-5
Bit Bit Bit
2
1
0
C h a n n e l-4
Bit Bit Bit
21
0
C h a n n e l-3
Bit Bit Bit
2
1
0
C h a n n e l-2
Bit Bit Bit
21
0
C h a n n e l-1
Bit Bit Bit
21
0
C h a n n e l-0
Bit Bit Bit
21
0
INT0 Register
Ch-7 Ch-6 Ch-5 Ch-4
Ch-
3
Ch-
2
Ch-1 Ch-0
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
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