XR16L788 Datasheet, PDF (23/42 Pages) Exar Corporation – HIGH PERFORMANCE OCTAL UART

XR16L788 OCTAL UART
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REV. 1.1.4
grammed trigger level. It will be cleared when the
FIFO drops below the programmed trigger level.
B. FIFO level will be reflected in the ISR register
when the FIFO trigger level is reached. Both the
ISR register status bit and the interrupt will be
cleared when the FIFO drops below the trigger
level.
C. The receive data ready bit (LSR BIT-0) is set as
soon as a character is transferred from the shift
register to the receive FIFO. It is reset when the
FIFO is empty.
4.10 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED
MODE OPERATION
When FCR BIT-0 equals a logic 1 for FIFO enable;
resetting IER bits 0-3 enables the XR16L788 in the
FIFO polled mode of operation. Since the receiver
and transmitter have separate bits in the LSR either
or both can be used in the polled mode by selecting
respective transmit or receive control bit(s).
A. LSR BIT-0 indicates there is data in RHR or RX
FIFO.
B. LSR BIT 1-4 provides the type of receive data er-
rors encountered for the data byte in RHR, if any.
C. LSR BIT-5 indicates THR is empty.
D. LSR BIT-6 indicates when both the transmit FIFO
and TSR are empty.
E. LSR BIT-7 indicates the Or’ed function of errors
in the RX FIFO.
IER[0]: RHR Interrupt Enable
The receive data ready interrupt will be issued when
RHR has a data character in the non-FIFO mode or
when the receive FIFO has reached the programmed
trigger level in the FIFO mode.
Logic 0 = Disable the receive data ready interrupt.
(default)
Logic 1 = Enable the receiver data ready interrupt.
IER[1]: THR Interrupt Enable
This interrupt is associated with bit-5 in the LSR reg-
ister. An interrupt is issued whenever the THR be-
comes empty or when data in the FIFO falls below
the programmed trigger level.
Logic 0 = Disable Transmit Holding Register empty
interrupt. (default)
Logic 1 = Enable Transmit Holding Register empty in-
terrupt.
IER[2]: Receive Line Status Interrupt Enable
Any of the LSR register bits 1,2,3 or 4 becomes ac-
tive will generate an interrupt to inform the host con-
troller about the error status of the current data byte
in FIFO.
Logic 0 = Disable the receiver line status interrupt.
(default)
Logic 1 = Enable the receiver line status interrupt.
IER[3]: Modem Status Interrupt Enable
Logic 0 = Disable the modem status register interrupt.
(default)
Logic 1 = Enable the modem status register interrupt.
IER[4]: Reserved.
IER[5]: Xoff Interrupt Enable (requires EFR bit-
4=1)
Logic 0 = Disable the software flow control, receive
Xoff interrupt. (default)
Logic 1 = Enable the software flow control, receive
Xoff interrupt. See Software Flow Control section for
details.
IER[6]: RTS# Output Interrupt Enable (requires
EFR bit-4=1)
Logic 0 = Disable the RTS# interrupt. (default).
Logic 1 = Enable the RTS# interrupt. The UART is-
sues an interrupt when the RTS# pin makes a transi-
tion.
IER[7]: CTS# Input Interrupt Enable (requires EFR
bit-4=1)
Logic 0 = Disable the CTS# interrupt. (default).
Logic 1 = Enable the CTS# interrupt. The UART is-
sues an interrupt when CTS# pin makes a transition.
4.11 INTERRUPT STATUS REGISTER (ISR)
The UART provides multiple levels of prioritized inter-
rupts to minimize external software interaction. The
Interrupt Status Register (ISR) provides the user with
six interrupt status bits. Performing a read cycle on
the ISR will give the user the current highest pending
interrupt level to be serviced, others queue up for
next service. No other interrupts are acknowledged
until the pending interrupt is serviced. The Interrupt
Source Table, Table 9, shows the data values (bit 0-5)
for the six prioritized interrupt levels and the interrupt
sources associated with each of these interrupt lev-
els.
4.11.1 Interrupt Generation:
• LSR is by any of the LSR bits 1, 2, 3 and 4.
• RXRDY is by RX trigger level.
• RXRDY Time-out is by the a 4-char plus 12 bits
delay timer if data doesn’t reach FIFO trigger level.
• TXRDY is by LSR bit-5 (or bit-6 in auto RS485 con-
trol).
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