XR16L788 Datasheet, PDF (21/42 Pages) Exar Corporation – HIGH PERFORMANCE OCTAL UART

XR16L788 OCTAL UART
REV. 1.1.4
FIGURE 12. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE
áç
Transm it
Data Byte
Flow Control Characters
(Xoff1/2 and Xon1/2 Reg.
Auto Software Flow Control
Transm it
FIFO
(64-Byte)
THR Interrupt (ISR bit-1) falls
below Program m ed Trigger
Level (TXTRG) and then
when becomes em pty. FIFO
is Enabled by FCR bit-0=1
16X or 8X Clock
(8XM ODE Register)
Transm it Data Shift Register
(TSR)
Auto CTS Flow Control (CTS# pin)
T X F IF O 1
4.7 RECEIVER
The receiver section contains an 8-bit Receive Shift
Register (RSR) and a byte-wide Receive Holding
Register (RHR). The RSR uses the 16X or 8X clock
for timing. It verifies and validates every bit on the in-
coming character in the middle of each data bit. On
the falling edge of a start or false start bit, an internal
receiver counter starts counting at the 16X (or 8X)
clock rate. After 8 (or 4) clocks the start bit period
should be at the center of the start bit. At this time the
start bit is sampled and if it is still a logic 0 it is validat-
ed. Evaluating the start bit in this manner prevents
the receiver from assembling a false character. The
rest of the data bits and stop bits are sampled and
validated in this same manner to prevent false fram-
ing. If there were any error(s), they are reported in the
LSR register bits 1- 4. Upon unloading the receive da-
ta byte from RHR, the receive FIFO pointer is
bumped and the error flags are immediately updated
to reflect the status of the data byte in RHR register.
RHR can generate a receive data ready interrupt up-
on receiving a character or delay until it reaches the
FIFO trigger level. Furthermore, data delivery to the
host is guaranteed by a receive data ready time-out
function when receive data does not reach the re-
ceive FIFO trigger level. This time-out delay is 4 word
lengths as defined by LCR[1,0] plus 12 bits time. The
RHR interrupt is enabled by IER bit-0.
4.8 REGISTERS
4.8.1 Receive Holding Register (RHR)
The receive holding register is a 8-bit register that
holds a receive data byte from the receive shift regis-
ter (RSR). It provides the receive data interface to the
host processor. The host reads the receive data byte
on this register whenever a data byte is transferred
from the RSR. RHR also part of the receive FIFO of
64 bytes by 11-bit wide, 3 extra bits are for the error
flags to be in LSR register. When the FIFO is enabled
by FCR bit-0, it acts as the first-out register of the
FIFO as new data are put over the first-in register. Ev-
ery time a read operation is made to the receive hold-
ing register, its FIFO data pointer is automatically
bumped to the next sequential data location. Also, the
error flags associated with the data byte are immedi-
ately updated onto the line status register (LSR) bits
1-4.
4.8.2 Baud Rate Generator Divisors (DLL and
DLM)
The Baud Rate Generator (BRG) is a 16-bit counter
that generates the data rate for the transmitter and re-
ceiver. The rate is programmed through registers DLL
and DLM which are only accessible when LCR bit-7 is
set to logic 1. See Programmable Baud Rate Genera-
tor section for more detail.
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