XR16L788 Datasheet, PDF (12/42 Pages) Exar Corporation – HIGH PERFORMANCE OCTAL UART

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XR16L788 OCTAL UART
REV. 1.1.4
identification. A return value of 0x28 from this register
indicates the device is a XR16L788. The DREV regis-
ter returns a 8-bit value of 0x01 for revision A, 0x02
for revision B and so on. This information is very use-
ful to the software driver for identifying which device it
is communicating with and to keep up with revision
changes.
DVID [7:0] default 0x28)
Device identification for the type of UART. The upper
nibble indicates it is a XR16L78x series with lower
nibble indicating the number of channels.
Examples:
XR16L788 = 0x28
XR16L784 = 0x24
externally between the XTAL1 and XTAL2 pins (see
Figure 6). Alternatively, an external clock can be con-
nected to the XTAL1 pin to clock the internal 8 baud
rate generators for standard or custom rates. Typical-
ly, the oscillator connections are shown in Figure 6.
For further reading on oscillator circuit please see ap-
plication note DAN108 on EXAR’s web site.
FIGURE 6. TYPICAL OSCILLATOR CONNECTIONS
R=300K to 400K
DREV [7:0] (default (0x01)
Revision number of the XR16L788. A 0x01 repre-
sents "revision-A" with 0x02 for rev-B and so forth.
1.1.8 REGB [7:0] (default 0x00)
REGB register provides a control for simultaneous
write to all 8 UARTs configuration registers or individ-
ually. This is very useful for device initialization in the
power up and reset routines.
REGB[0]
REGB[7:1]
Logic 0 (default) write to each UART
configuration registers individually.
Logic 1 enables simultaneous write to
all 8 UARTs configuration register. Use-
ful during device initialization.
Reserved
2.0 CRYSTAL OSCILLATOR / BUFFER
The 788 includes an on-chip oscillator (XTAL1 and
XTAL2). The crystal oscillator provides the system
clock to the Baud Rate Generators (BRG) in each of
the 8 UARTs, the 16-bit general purpose timer/
counter and internal logics. XTAL1 is the input to the
oscillator or external clock buffer input with XTAL2 pin
being the output. For programming details, see “Pro-
grammable Baud Rate Generator” on page 13.
The on-chip oscillator is designed to use an industry
standard microprocessor crystal (parallel resonant
with 10-22 pF capacitance load, 100ppm) connected
XTAL1 14.7456 XTAL2
MHz
C1
22-47pF
C2
22-47pF
3.0 TRANSMIT AND RECEIVE DATA
Each UART channel has a transmit holding register
(THR) and a receive holding register (RHR). The
THR and RHR registers are 16550 compatible so
their access is limited to 8-bit format. The software
driver must separately read the LSR content for the
associated error flags before reading the data byte.
3.1 FIFO DATA LOADING AND UNLOADING
THROUGH THE UART CHANNEL REGIS-
TERS, THR AND RHR.
The THR and RHR register addresses for channel 0
to channel 7 is shown in Table 5 below. The THR and
RHR for channels 0 to 7 are located at address 0x00,
0x10, 0x20, 0x30, 0x40, 0x50, 0x60 and 0x70 respec-
tively. Transmit data byte is loaded to the THR when
writing to that address and receive data is unloaded
from the RHR register when reading that address.
Both THR and RHR registers are 16C550 compatible
in 8-bit format, so each bus operation can only write
or read in bytes.
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