XR16L788 Datasheet, PDF (13/42 Pages) Exar Corporation – HIGH PERFORMANCE OCTAL UART

XR16L788 OCTAL UART
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REV. 1.1.4
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TABLE 5: TRANSMIT AND RECEIVE DATA REGISTER, 16C550 COMPATIBLE
THR and RHR Address Locations For CH0 to CH7 (16C550 Com patible)
C H0 0x00 W rite TH R Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
C H0 0x00 Read R H R Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
C H1 0x10 W rite TH R Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
C H1 0x10 Read R H R Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
C H2 0x20 W rite TH R Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
C H2 0x20 Read R H R Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
C H3 0x30 W rite TH R Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
C H3 0x30 Read R H R Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
C H4 0x40 W rite TH R Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
C H4 0x40 Read R H R Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
C H5 0x50 W rite TH R Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
C H5 0x50 Read R H R Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
C H6 0x60 W rite TH R Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
C H6 0x60 Read R H R Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
C H7 0x70 W rite TH R Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
CH7 0x70 Read RHR
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
THRRHR1
4.0 UART
There are 8 UARTs [channel 7:0] in the 788. Each
has its own 64-byte of transmit and receive FIFO, a
set of 16550 compatible control and status registers,
and a baud rate generator for individual channel data
rate setting. Eight additional registers per UART were
added for the EXAR enhanced features.
4.1 PROGRAMMABLE BAUD RATE GENERATOR
Each UART has its own Baud Rate Generator (BRG)
with a prescaler for the transmitter and receiver. The
prescaler is controlled by a software bit in the MCR
register. The MCR register bit-7 sets the prescaler to
divide the input crystal or external clock by 1 or 4. The
output of the prescaler clocks to the BRG. The BRG
further divides this clock by a programmable divisor
between 1 and (2¹⁶ -1) to obtain a 16X or 8X sam-
pling clock of the serial data rate. The sampling clock
is used by the transmitter for data bit shifting and re-
ceiver for data sampling. The BRG divisor (DLL and
DLM registers) defaults to a random value upon pow-
er up. Therefore, the BRG must be programmed dur-
ing initialization to the operating data rate.
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