XR16L788 Datasheet, PDF (22/42 Pages) Exar Corporation – HIGH PERFORMANCE OCTAL UART

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FIGURE 13. RECEIVER OPERATION IN NON-FIFO MODE
XR16L788 OCTAL UART
REV. 1.1.4
16X or 8X C lock
(8XM O D E R egister)
R eceive D ata Shift
R egister (R SR )
D ata Bit
V alidation
R eceive D ata C haracters
R eceive
Data Byte
and Errors
E rro r
Flags in
LSR bits
4:2
R eceive D ata
H olding Register
(R H R )
R H R Interrupt (ISR bit-2)
R X F IF O 1
FIGURE 14. RECEIVER OPERATION IN FIFO AND FLOW CONTROL MODE
16X or 8X Sam pling
Clock (8XM ODE Reg.)
64 bytes by 11-
bit w ide FIFO
Receive Data
Byte and Errors
Receive Data Shift
Register (RSR)
Receive Data
FIFO
(6 4 -b y te )
R e c e ive
D a ta
Data Bit
V a lid a tio n
Receive Data Characters
Exam ple:
- FIFO trigger level set at 48 bytes
- R TS/D TR hyasteresis set at +/-8 chars.
Data falls to 40 ^{RT S#/DT R# re-asserts when data falls below}
the trigger level to restart rem ote transm itter.
Enable by EFR bit-6=1, M CR bit-2.
FIFO Trigger=48 ^{RHR Interrupt (ISR bit-2) is program m ed}
at FIFO trigger level (RXTRG ).
FIFO is Enable by FC R bit-0=1
Data fills to 56 ^{RT S#/DT R# de-asserts when data fills above}
the trigger level to suspend rem ote transm itter.
Enable by EFR bit-6=1, M CR bit-2.
RXFIFO 1
4.8.3 Interrupt Enable Register (IER)
The Interrupt Enable Register (IER) masks the inter-
rupts from receive data ready, transmit empty, line
status and modem status registers. These interrupts
are reported in the Interrupt Status Register (ISR)
register and also encoded in INT (INT0-INT3) register
in the Device Configuration Registers.
4.9 IER VERSUS RECEIVE FIFO INTERRUPT MODE
OPERATION
When the receive FIFO (FCR BIT-0 = a logic 1) and
receive interrupts (IER BIT-0 = logic 1) are enabled,
the RHR interrupts (see ISR bits 3 and 4) status will
reflect the following:
A. The receive data available interrupts are issued
to the host when the FIFO has reached the pro-
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