XR16L788 Datasheet, PDF (41/42 Pages) Exar Corporation – HIGH PERFORMANCE OCTAL UART

XR17C158
PCI BUS OCTAL UART
REV. 1.1.4
TABLE OF CONTENTS
áç
GENERAL DESCRIPTION ............................................................................................... 1
APPLICATIONS ........................................................................................................................................... 1
NEW FEATURES: ...................................................................................................................................... 1
Figure 1. Block Diagram ......................................................................................................................... 1
Figure 2. Pin Out of the Device .............................................................................................................. 2
ORDERING INFORMATION ............................................................................................................................ 2
PIN DESCRIPTIONS ....................................................................................................... 3
DESCRIPTION .................................................................................................................. 7
1.0 XR16L788 REGISTERS ......................................................................................................................... 7
Figure 3. The XR16L788 Registers ........................................................................................................ 7
1.1 DEVICE CONFIGURATION REGISTER SET ................................................................................... 7
TABLE 1: XR16L788 REGISTER SETS ....................................................................................................... 8
TABLE 2: DEVICE CONFIGURATION REGISTERS .......................................................................................... 8
INT0 Channel Interrupt Indicator: ....................................................................................... 9
INT1, INT2 and INT3 Interrupt Source Locator ................................................................. 9
Figure 4. The Global Interrupt Registers, INT0, INT1, INT2 and INT3 ................................................... 9
TABLE 3: UART CHANNEL [7:0] INTERRUPT SOURCE ENCODING AND CLEARING ...................................... 10
Figure 5. Timer/Counter circuit. ............................................................................................................ 10
TABLE 4: TIMER CONTROL REGISTER ................................................................................................. 10
2.0 CRYSTAL OSCILLATOR / BUFFER .................................................................................................... 12
3.0 TRANSMIT AND RECEIVE DATA ........................................................................................................ 12
3.1 FIFO DATA LOADING AND UNLOADING THROUGH THE UART CHANNEL REGISTERS, THR AND RHR. 12
Figure 6. Typical oscillator connections ................................................................................................ 12
TABLE 5: TRANSMIT AND RECEIVE DATA REGISTER, 16C550 COMPATIBLE ............................................... 13
4.0 UART ..................................................................................................................................................... 13
4.1 PROGRAMMABLE BAUD RATE GENERATOR ........................................................................................................... 13
Figure 7. Baud Rate Generator ............................................................................................................ 14
TABLE 6: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK AT 16X SAMPLING ... 14
4.2 AUTOMATIC RTS/DTR HARDWARE FLOW CONTROL OPERATION ........................................................................... 14
Figure 8. Auto RTS/DTR and CTS/DSR Flow Control Operation ......................................................... 15
4.3 INFRARED MODE .................................................................................................................................................. 16
Figure 9. Infrared Transmit Data Encoding and Receive Data Decoding ............................................. 16
4.4 INTERNAL LOOPBACK ........................................................................................................................................... 16
Figure 10. Internal Loop Back .............................................................................................................. 17
4.5 UART CHANNEL CONFIGURATION REGISTERS AND ADDRESS DECODING. ......................................... 17
TABLE 7: UART CHANNEL CONFIGURATION REGISTERS. ............................................................. 18
TABLE 8: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED BY
EFR BIT-4. ............................................................................................................................................. 19
4.6 TRANSMITTER ...................................................................................................................................................... 20
Figure 11. Transmitter Operation in non-FIFO Mode ........................................................................... 20
Figure 12. Transmitter Operation in FIFO and Flow Control Mode ...................................................... 21
4.7 RECEIVER ........................................................................................................................................................... 21
4.8 REGISTERS .......................................................................................................................................................... 21
Figure 13. Receiver Operation in non-FIFO Mode ............................................................................... 22
Figure 14. Receiver Operation in FIFO and Flow Control Mode .......................................................... 22
4.9 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION .................................................................................. 22
4.10 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION ..................................................................... 23
4.11 INTERRUPT STATUS REGISTER (ISR) .................................................................................................................. 23
TABLE 9: INTERRUPT SOURCE AND PRIORITY LEVEL ................................................................................ 24
TABLE 10: TRANSMIT AND RECEIVE FIFO TRIGGER LEVEL SELECTION ..................................................... 25
TABLE 11: PARITY SELECTION ................................................................................................................. 26
TABLE 12: AUTO RS485 HALF-DUPLEX DIRECTION CONTROL DELAY FROM TRANSMIT-TO-RECEIVE .......... 29
I