XR16L788 Datasheet, PDF (20/42 Pages) Exar Corporation – HIGH PERFORMANCE OCTAL UART

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XR16L788 OCTAL UART
REV. 1.1.4
NOTE 2: MCR bits 2 and 3 (OP1 and OP2 outputs) are not
available in the XR16L788. They are present for 16C550
compatibility during Internal loopback, see Figure 10.
4.6 TRANSMITTER
The transmitter section comprises of 64 bytes of
FIFO, a byte-wide Transmit Holding Register (THR)
and an 8-bit Transmit Shift Register (TSR). THR re-
ceives a data byte from the host (non-FIFO mode) or
a data byte from the FIFO when the FIFO is enabled
by FCR bit-0. TSR shifts out every data bit with the
16X or 8X internal clock. A bit time is 16 or 8 clock pe-
riods. The transmitter sends the start bit followed by
the number of data bits, inserts the proper parity bit if
enabled, and adds the stop bit(s). The status of the
THR and TSR are reported in the Line Status Regis-
ter (LSR bit-5 and bit-6).
4.6.1 Transmit Holding Register (THR)
The transmit holding register is an 8-bit register pro-
viding a data interface to the host processor. The host
writes transmit data byte to the THR to be converted
into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (Bit-
0) becomes first data bit to go out. The THR is also
the input register to the transmit FIFO of 64 bytes
when FIFO operation is enabled by FCR bit-0. Every
time a write operation is made to the transmit holding
register, its FIFO data pointer is automatically
bumped to the next sequential data location. A THR
empty interrupt can be generated when IER bit-1 is
set to logical 1.
4.6.2 Transmitter Operation in non-FIFO
The host loads transmit data to THR one character at
a time. The THR empty flag (LSR bit-5) is set when
the data byte is transferred to TSR. THR flag can
generate a transmit empty interrupt (ISR bit-1) when
it is enabled by IER bit-1. The TSR flag (LSR bit-6) is
set when TSR becomes completely empty.
FIGURE 11. TRANSMITTER OPERATION IN NON-FIFO MODE
Data
Byte
16X or 8X
Clock
(8XMODE
Register)
Transmit
Holding
Register
(THR)
THR Interrupt (ISR bit-1)
Enabled by IER bit-1
Transmit Shift Register (TSR)
M
L
S
S
B
B
TXNOFIFO1
4.6.3 Transmitter Operation in FIFO
The host may fill the transmit FIFO with up to 64
bytes of transmit data. The THR empty flag (LSR bit-
5) is set whenever the FIFO is empty. The THR emp-
ty flag can generate a transmit empty interrupt (ISR
bit-1) when the amount of data in the FIFO falls below
its programmed trigger level (see TXTRG register).
The transmit empty interrupt is enabled by IER bit-1.
The TSR flag (LSR bit-6) is set when TSR becomes
completely empty. Furthermore, with the RS485 half-
duplex direction control enabled (FCTR bit-5=1), the
source of the transmit empty interrupt changes to
TSR empty instead of THR empty. This is to ensure
the RTS# output is not changed until the last stop bit
of the last character is shifted out.
4.6.4 Auto RS485 Operation
The auto RS485 half-duplex direction control chang-
es the behavior of the transmitter when enabled by
FCTR bit-5. It de-asserts RTS# or DTR# after a spec-
ified delay indicated in MSR[7:4] following the last
stop bit of the last character that has been transmit-
ted. This helps in turning around the transceiver to re-
ceive the remote station’s response. The delay opti-
mizes the time needed for the last transmission to
reach the farthest station on a long cable network be-
fore switching off the line driver. This delay prevents
undesirable line signal disturbance that causes signal
degradation. The auto RS485 half-duplex direction
control also changes the transmitter empty interrupt
to TSR empty instead of THR empty.
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