XR16L788 Datasheet, PDF (29/42 Pages) Exar Corporation – HIGH PERFORMANCE OCTAL UART

XR16L788 OCTAL UART
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REV. 1.1.4
TABLE 12: AUTO RS485 HALF-DUPLEX DIRECTION CONTROL DELAY FROM TRANSMIT-TO-RECEIVE
MSR[7]
0
0
0
0
0
9
0
0
1
1
1
1
1
1
1
1
MSR[6]
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
MSR[5]
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
MSR[4]
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DELAY IN DATA BIT(S) TIME
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCRATCH PAD REGISTER (SPR)
This is a 8-bit general purpose register for the user to
store temporary data. The content of this register is
preserved during sleep mode but becomes 0xFF (de-
fault) after a reset or a power off-on cycle.
FEATURE CONTROL REGISTER (FCTR)
This register controls the UART enhanced functions
that are not available on ST16C554 or ST16C654.
FCTR [3:0] - Auto RTS/DTR Flow Control Hystere-
sis Select
These bits select the auto RTS/DTR flow control hys-
teresis and only valid when TX and RX Trigger Table-
D is selected (FCTR bit-6 and 7 are set to logic 1).
The RTS/DTR hysteresis is referenced to the RX
FIFO trigger level. After reset, these bits are set to
logic 0 selecting the next FIFO trigger level for hard-
ware flow control. Table 13 below shows the 16 select-
able hysteresis levels.
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