XR16L788 Datasheet, PDF (11/42 Pages) Exar Corporation – HIGH PERFORMANCE OCTAL UART

XR16L788 OCTAL UART
REV. 1.1.4
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TIMERCNTL Register
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
Rsvd
Rsvd
Rsvd
Rsvd
Clock Single/ Start/ INT
Select Re-trigger Stop Enable
TIMER [7:0] (default 0x00): Reserved.
TIMERMSB [7:0] and TIMERLSB [7:0]
TIMERMSB and TIMERLSB form a 16-bit value. The
least-significant bit of the timer is being bit [0] of the
TIMERLSB with most-significant-bit being bit [7] in
TIMERMSB. Reading the TIMERCNTL register will
clear its interrupt. Default value is zero upon power-
up and reset.
16-Bit Tim er/Counter Program m able Registers
TIMERMSB Register
TIMERLSB Register
Bit-15 Bit-14 Bit-13 Bit-12 Bit-11 Bit-10 Bit-9 Bit-8
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
1.1.3 8XMODE [7:0] (default 0x00)
Each bit selects 8X or 16X sampling rate for that
UART channel, bit-0 is channel 0. Logic 0 (default)
selects normal 16X sampling with logic one selects
8X sampling rate. Transmit and receive data rates will
double by selecting 8X.
8XMODE Register
Individual UART Channel 8X Clock Mode Enable
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
Ch-7 Ch-6 Ch-5 Ch-4 Ch-3 Ch-2 Ch-1 Ch-0
1.1.4 REGA [15:8] is reserved (default 0x00)
REGA [7:0] IS RESERVED
(default 0x00)
logic 1 to perform a reset to that channel. All registers
in that channel will be reset to the default condition,
see Table 15 for details. As an example, bit-0 =1 re-
sets UART channel 0 with bit-7=1 resets channel 7.
1.1.6 SLEEP [7:0] (default 0x00)
The 8-bit Sleep register enables each UART sepa-
rately to enter Sleep mode. Sleep mode reduces
power consumption when the system needs to put
the UART(s) to idle. The UART enters sleep mode
when there is no interrupt pending. When all 8 UARTs
are put to sleep, the on-chip oscillator shuts off to fur-
ther conserve power. In this case, the octal UART is
awaken by any of the UART channel on from a re-
ceive data byte or a change on the serial port. The
UART is ready after 32 crystal clocks to ensure full
functionality. Also, a special interrupt is generated
with an indication of no pending interrupt. Logic 0 (de-
fault) and logic 1 disable and enable sleep mode re-
spectively.
1.1.5 RESET [7:0] (default 0x00)
RESET Register
Individual UART Channel Reset Enable
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
Ch-7 Ch-6 Ch-5 Ch-4 Ch-3 Ch-2 Ch-1 Ch-0
SLEEP Register
Individual UART Channel Sleep Enable
Ch-7 Ch-6 Ch-5 Ch-4 Ch-3 Ch-2 Ch-1 Ch-0
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
The 8-bit Reset register [RESET] provides the soft-
ware with the ability to reset the UART(s) when there
is a need. Each bit is self-resetting after it is written a
1.1.7 Device Identification and Revision
There are 2 internal registers that provide device
identification and revision, DVID and DREV registers.
The 8-bit content in the DVID register provides device
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