XRT83L38 Datasheet, PDF (89/91 Pages) Exar Corporation – OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
ORDERING INFORMATION
PART NUMBER
XRT83L38IV
XRT83L38IB
PACKAGE
208 Pin TQFP(28 x 28 x 1.4 mm)
225 Ball BGA
OPERATING TEMPERATURE RANGE
-40^°C to +85^°C
-40^°C to +85^°C
REVISIONS
REVISION #
A1.0.0 thru
A1.0.5
P1.1.0
P1.1.1
P1.2.0
P1.2.1
P1.2.2
P1.2.3
P1.2.4
P1.2.5
P1.2.6
P1.2.7
P1.2.8
P1.2.9
P1.3.0
P1.3.1
P1.3.2
DATE
Advanced versions.
DESCRIPTION
9/01
5/02
6/02
7/02
8/02
10/02
10/02
Preliminary release with modified register tables.
Corrected description of RXTSEL pin 83. ...by setting the TERCNTL bit (bit 6) to...
Added SL_1, SL_0, EQG_1 and EQG_0 to Control Global Register 131. Separated
Microprocessor description table by register number. Moved absolute maximum and DC
electrical characteristics before AC electrical characteristics. Replaced TBD’s in electrical
tables. Reformated table of contents.
Added GAUGE1 and GAUGE0 to Control Global Register 131. Corrected control register
binary bits.
Renamed FIFO pin to GAUGE, edited definition and edited definition of JASEL[1:0] to
reflect the FIFO size is selected by the jitter attenuator select.
Redefined bits D3, D2 and D0 of register 1, in combination these bits set the jitter attenu-
ator path and FIFO size.
Corrected pin list, pin 114 was listed as GND and DMO_6. Pin 114 is DMO_6. Revised
JASEL1 and JASEL0 table in pin list to show JABW and FIFO size. Re-redefined bits D3,
D2 and D0 of register 1, in combination these bits set the jitter attenuator path and FIFO
size. Added Jitter attenuator tables in microprocessor register tables. Modified micropro-
cessor descriptions, timing diagrams and electrical characteristics.
Replaced GCHIE with Reserved in Tables 18, 23, 24,25. In the pin list description for INT,
replace IMASK bit to a “1” with GIE bit to a “0”.
New description for bits D6 - D0 in Tables 27 - 34 Microprocessor Registers. Corrected
TXON_n pins to be internally pulled-down.
Revised Microprocessor interface timing diagrams and data.
Corrected microprocessor timing information and edited Redundancy section.
Edited section on RLOS, TGND changed to AGND, RGND changed to ExVCM, T1 LOS
from 45dB to 36dB. Corrected references to transformer ratios of receiver from 2:1 to 1:1
and transmitter 1:2 internal and 1:2.45 external termination.
Minor text editing.
AGND Changed back to TGND, ExVCM changed back to RGND. Changed RXRES1 and
RXRES0, Required Fixed External Rx Resistor Values, to 4x previous values. Added 225
ball BGA package. Added description of arbitrary pulse and Gap Clock support.
Minor edits to block diagram, changed issue date to January, corrected register 67 in table
18, corrected table 37.
85