XRT83L38 Datasheet, PDF (73/91 Pages) Exar Corporation – OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
TABLE 37: MICROPROCESSOR REGISTER #130, BIT DESCRIPTION
REGISTER ADDRESS
10000010
BIT #
NAME
FUNCTION
REGISTER
TYPE
RESET
VALUE
D7
TXONCNTL Transmit On Control:
R/W
0
In Host mode, setting this bit to “1” transfers the control of the
Transmit On/Off function to the TXON_n Hardware control
pins.
NOTE: This provides a faster On/Off capability for redundancy
application.
D6
TERCNTL Termination Control.
R/W
0
In Host mode, setting this bit to “1” transfers the control of the
RXTSEL to the RXTSEL Hardware control pin.
NOTE: This provides a faster On/Off capability for redundancy
application.
D5-D4
Reserved
69