XRT83L38 Datasheet, PDF (18/91 Pages) Exar Corporation – OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
JITTER ATTENUATOR
SIGNAL
NAME
JASEL0
JASEL1
TQFP
PIN #
167
168
BGA
LEAD #
A14
B13
TYPE
DESCRIPTION
Jitter Attenuator Select Pins Hardware Mode
I Jitter Attenuator select Bit 0
Jitter Attenuator select Bit 1
JASEL[1:0] pins are used to place the jitter attenuator in the transmit path, the
receive path or to disable it.
JASEL1 JASEL0 JA Path
0
0
Disabled
0
1
Transmit
1
0
Receive
1
1
Receive
JA BW Hz
T1
E1
----- -----
3
10
3
10
3
1.5
FIFO Size
--------
32/32
32/32
64/64
NOTE: These pins are internally pulled “Low” with 50kΩ resistors.
CLOCK SYNTHESIZER
SIGNAL
NAME
MCLKOUT
MCLKT1
MCLKE1
TQFP
PIN #
BGA
LEAD #
TYPE
DESCRIPTION
23
H1
O Synthesized Master Clock Output
This signal is the output of the Master Clock Synthesizer PLL which is at T1 or
E1 rate based upon the mode of operation.
27
K1
I T1 Master Clock Input
This signal is an independent 1.544MHz clock for T1 systems with accuracy
better than ±50ppm and duty cycle within 40% to 60%. MCLKT1 is used in the
T1 mode.
NOTES:
1. All channels of the XRT83L38 must be operated at the same clock
rate, either T1, E1 or J1.
2. See pin 26 description for further explanation for the usage of this pin.
3. Internally pulled “Low” with a 50kΩ resistor.
26
J1
I E1 Master Clock Input
A 2.048MHz clock for with an accuracy of better than ±50ppm and a duty cycle
of 40% to 60% can be provided at this pin.
In systems that have only one master clock source available (E1 or T1), that
clock should be connected to both MCLKE1 and MCLKT1 inputs for proper
operation.
NOTES:
1. All channels of the XRT83L38 must be operated at the same clock
rate, either T1, E1 or J1.
2. Internally pulled “Low” with a 50kΩ resistor.
14