XRT83L38 Datasheet, PDF (61/91 Pages) Exar Corporation – OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
TABLE 23: MICROPROCESSOR REGISTER #4, BIT DESCRIPTION
REGISTER ADDRESS
00000100
00010100
00100100
00110100
01000100
01010100
01100100
01110100
CHANNEL_n
CHANNEL_0
CHANNEL_1
CHANNEL_2
CHANNEL_3
CHANNEL_4
CHANNEL_5
CHANNEL_6
CHANNEL_7
FUNCTION
REGISTER
TYPE
RESET
VALUE
BIT #
D7
D6
D5
D4
D3
D2
D1
D0
NAME
Reserved
RO
0
DMOIE_n DMO Interrupt Enable: Writing a “1” to this bit enables DMO R/W
0
interrupt generation, writing a “0” masks it.
FLSIE_n FIFO Limit Status Interrupt Enable: Writing a “1” to this bit
R/W
0
enables interrupt generation when the FIFO limit is within to 3
bits, writing a “0” to masks it.
LCVIE_n Line Code Violation Interrupt Enable: Writing a “1” to this bit R/W
0
enables Line Code Violation interrupt generation, writing a “0”
masks it.
NLCDIE_n Network Loop-Code Detection Interrupt Enable: Writing a R/W
0
“1” to this bit enables Network Loop-code detection interrupt
generation, writing a “0” masks it.
AISDIE_n AIS Interrupt Enable: Writing a “1” to this bit enables Alarm
R/W
0
Indication Signal detection interrupt generation, writing a “0”
masks it.
RLOSIE_n Receive Loss of Signal Interrupt Enable: Writing a “1” to this R/W
0
bit enables Loss of Receive Signal interrupt generation, writing
a “0” masks it.
QRPDIE_n QRSS Pattern Detection Interrupt Enable: Writing a “1” to
R/W
0
this bit enables QRSS pattern detection interrupt generation,
writing a “0” masks it.
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