XRT83L38 Datasheet, PDF (15/91 Pages) Exar Corporation – OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
MICROPROCESSOR INTERFACE
SIGNAL NAME
HW_HOST
WR_R/W
EQC0
RD_DS
EQC1
ALE_AS
EQC2
CS
EQC3
TQFP
PIN #
BGA
LEAD
#
TYPE
DESCRIPTION
80 T10 I Mode Control Input
This pin selects Hardware or Host mode. Leave this pin unconnected or tie
“High” to select Hardware mode.
For Host mode, this pin must be tied “Low”.
NOTE: Internally pulled “High” with a 50kΩ resistor.
190 D7
190 D7
I Write Input (Read/Write) - Host mode:
Intel bus timing: A “Low” pulse on WR selects a write operation when CS pin
is “Low”.
Motorola bus timing: A “High” pulse on R/W selects a read operation and a
“Low” pulse on R/W selects a write operation when CS is “Low”.
Equalizer Control Input pin 0 - Hardware mode
Pins EQC0, EQC1, EQC2, EQC3 and EQC4 select the Receive Equalizer and
Transmitter Line Build Out. See “Receive Equalizer Control and Transmit Line
Build-Out Settings” on page 30.
NOTE: Internally pulled “Low” with a 50kΩ resistor.
191 C7
191 C7
I Read Input (Data Strobe) - Host mode
Intel bus timing: A “Low” pulse on RD selects a read operation when the CS
pin is “Low”.
Motorola bus timing: A “Low” pulse on DS indicates a read or write operation
when the CS pin is “Low”.
Equalizer Control Input pin 1 - Hardware mode
Pins EQC0, EQC1, EQC2, EQC3 and EQC4 select the Receive Equalizer and
Transmitter Line Build Out. See “Receive Equalizer Control and Transmit Line
Build-Out Settings” on page 30.
NOTE: Internally pulled “Low” with a 50kΩ resistor.
192 A7 I Address Latch Input (Address Strobe) - Host mode
Intel bus timing: The address inputs are latched into the internal register on
the falling edge of ALE.
Motorola bus timing: The address inputs are latched into the internal register
on the falling edge of AS.
192 A7
Equalizer Control Input pin 2 - Hardware mode
Pins EQC0, EQC1, EQC2, EQC3 and EQC4 select the Receive Equalizer and
Transmitter Line Build Out. See “Receive Equalizer Control and Transmit Line
Build-Out Settings” on page 30.
NOTE: Internally pulled “Low” with a 50kΩ resistor.
193 B7 I Chip Select Input - Host mode:
This signal must be “Low” in order to access the parallel port.
193 B7
Equalizer Control Input pin 3 - Hardware mode:
Pins EQC0, EQC1, EQC2, EQC3 and EQC4 select the Receive Equalizer and
Transmitter Line Build Out. See “Receive Equalizer Control and Transmit Line
Build-Out Settings” on page 30.
NOTE: Internally pulled “Low” with a 50kΩ resistor.
11