XRT83L38 Datasheet, PDF (50/91 Pages) Exar Corporation – OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
MICROPROCESSOR REGISTER TABLES
The microprocessor interface consists of 256 addressable locations. Each channel uses 16 dedicated 8 byte
registers for independent programming and control. There are four additional registers for global control of all
channels and two registers for device identification and revision numbers. The remaining registers are for
factory test and future expansion. The control register map and the function of the individual bits are
summarized in Table 17 and Table 18 respectively.
REGISTER NUMBER
0 - 15
16 - 31
32 - 47
48 - 63
64 - 79
80 - 95
96-111
112 - 127
128 - 131
132 -139
140 - 191
192
193 - 195
196 - 203
204 - 253
254
255
TABLE 17: MICROPROCESSOR REGISTER ADDRESS
REGISTER ADDRESS
HEX
BINARY
FUNCTION
0x00 - 0x0F
00000000 - 00001111 Channel 0 Control Registers
0x10 -0x1F
00010000 - 00011111 Channel 1 Control Registers
0x20 - 0x2F
00100000 - 00101111 Channel 2 Control Registers
0x30 - 0x3F
00110000 - 00111111 Channel 3 Control Registers
0x40 - 0x4F
01000000 - 01001111 Channel 4 Control Registers
0x50 - 0x5F
01010000 - 01011111 Channel 5 Control Registers
0x60 - 0x6F
01100000 - 01101111 Channel 6 Control Registers
0x70 - 0x7F
01110000 - 01111111 Channel 7 Control Registers
0x80 - 0x83
10000000 - 10000011 Command Control registers for all 8 channels
0x84 - 0x8B
10000100 - 10001011 R/W registers reserved for testing channels 0-3
0x8C - 0xBF
10001100 - 10111111 Reserved
0xC0
11000000
Command Control register for all 8 channels
0xC1 - 0xC3
11000001 - 11000011 Reserved
0xC4 - 0xCB
11000100 - 11001011 R/W registers reserved for testing channels 4-7
0xCC - 0xFD
11001100 - 11111101 Reserved
0xFE
11111110
Device “ID”
0xFF
11111111
Device “Revision ID”
TABLE 18: MICROPROCESSOR REGISTER BIT DESCRIPTION
REG. #
ADDRESS
REG.
TYPE
BIT 7
BIT 6
BIT 5
BIT 4
Channel 0 Control Registers
0
00000000 R/W Reserved Reserved
RXON_n
Hex 0x00
EQC4_n
1
00000001 R/W RXTSEL_n TXTSEL_n TERSEL1_n TERSEL0_n
Hex 0x01
2
00000010 R/W INVQRSS_n TXTEST2_n TXTEST1_n TXTEST0_n
Hex 0x02
BIT 3
EQC3_n
JASEL1_n
TXON_n
BIT 2
EQC2_n
JASEL0_n
LOOP2_n
BIT 1
EQC1_n
JABW_n
LOOP1_n
BIT 0
EQC0_n
FIFOS_n
LOOP0_n
46