XRT83L38 Datasheet, PDF (7/91 Pages) Exar Corporation – OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
Internal Receive Termination Mode.........................................................................................................31
TABLE 6: RECEIVE TERMINATION CONTROL .............................................................................................................. 32
FIGURE 13. SIMPLIFIED DIAGRAM FOR THE INTERNAL RECEIVE AND TRANSMIT TERMINATION MODE ........................... 32
TABLE 7: RECEIVE TERMINATIONS ............................................................................................................................ 32
FIGURE 14. SIMPLIFIED DIAGRAM FOR T1 IN THE EXTERNAL TERMINATION MODE (RXTSEL= 0)................................ 33
TRANSMITTER (CHANNELS 0 - 7) .............................................................................................. 34
Transmit Termination Mode.....................................................................................................................34
External Transmit Termination Mode ......................................................................................................34
FIGURE 15. SIMPLIFIED DIAGRAM FOR E1 IN EXTERNAL TERMINATION MODE (RXTSEL= 0) ...................................... 34
TABLE 8: TRANSMIT TERMINATION CONTROL ............................................................................................................ 34
TABLE 9: TERMINATION SELECT CONTROL................................................................................................................ 34
REDUNDANCY APPLICATIONS............................................................................................... 35
TABLE 10: TRANSMIT TERMINATION CONTROL .......................................................................................................... 35
TABLE 11: TRANSMIT TERMINATIONS ........................................................................................................................ 35
TYPICAL REDUNDANCY SCHEMES ....................................................................................... 36
FIGURE 16. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT SECTION FOR 1:1 & 1+1 REDUNDANCY .......................... 37
FIGURE 17. SIMPLIFIED BLOCK DIAGRAM - RECEIVE SECTION FOR 1:1 AND 1+1 REDUNDANCY .................................. 37
FIGURE 18. SIMPLIFIED BLOCK DIAGRAM - TRANSMIT SECTION FOR N+1 REDUNDANCY............................................. 38
FIGURE 19. SIMPLIFIED BLOCK DIAGRAM - RECEIVE SECTION FOR N+1 REDUNDANCY............................................... 39
PATTERN TRANSMIT AND DETECT FUNCTION................................................................................. 40
TRANSMIT ALL ONES (TAOS)....................................................................................................... 40
NETWORK LOOP CODE DETECTION AND TRANSMISSION ................................................................ 40
TABLE 12: PATTERN TRANSMISSION CONTROL .......................................................................................................... 40
TABLE 13: LOOP-CODE DETECTION CONTROL .......................................................................................................... 40
TRANSMIT AND DETECT QUASI-RANDOM SIGNAL SOURCE (TDQRSS)........................................... 41
LOOP-BACK MODES ..................................................................................................................... 42
LOCAL ANALOG LOOP-BACK (ALOOP) ......................................................................................... 42
TABLE 14: LOOP-BACK CONTROL IN HARDWARE MODE .............................................................................................. 42
TABLE 15: LOOP-BACK CONTROL IN HOST MODE....................................................................................................... 42
FIGURE 20. LOCAL ANALOG LOOP-BACK SIGNAL FLOW .............................................................................................. 42
REMOTE LOOP-BACK (RLOOP).................................................................................................... 43
FIGURE 21. REMOTE LOOP-BACK MODE WITH JITTER ATTENUATOR SELECTED IN RECEIVE PATH.................................. 43
FIGURE 22. REMOTE LOOP-BACK MODE WITH JITTER ATTENUATOR SELECTED IN TRANSMIT PATH ............................... 43
DIGITAL LOOP-BACK (DLOOP)..................................................................................................... 44
DUAL LOOP-BACK ........................................................................................................................ 44
FIGURE 23. DIGITAL LOOP-BACK MODE WITH JITTER ATTENUATOR SELECTED IN TRANSMIT PATH ................................ 44
FIGURE 24. SIGNAL FLOW IN DUAL LOOP-BACK MODE ............................................................................................... 44
MICROPROCESSOR PARALLEL INTERFACE..............................................................45
TABLE 16: MICROPROCESSOR INTERFACE SIGNAL DESCRIPTION ................................................................................ 45
MICROPROCESSOR REGISTER TABLES .......................................................................................... 46
TABLE 17: MICROPROCESSOR REGISTER ADDRESS .................................................................................................. 46
TABLE 18: MICROPROCESSOR REGISTER BIT DESCRIPTION ...................................................................................... 46
MICROPROCESSOR REGISTER DESCRIPTIONS ............................................................................... 50
TABLE 19: MICROPROCESSOR REGISTER #0, BIT DESCRIPTION ................................................................................ 50
TABLE 20: MICROPROCESSOR REGISTER #1, BIT DESCRIPTION ................................................................................ 51
TABLE 21: MICROPROCESSOR REGISTER #2, BIT DESCRIPTION ................................................................................ 53
TABLE 22: MICROPROCESSOR REGISTER #3, BIT DESCRIPTION ................................................................................ 55
TABLE 23: MICROPROCESSOR REGISTER #4, BIT DESCRIPTION ................................................................................ 57
TABLE 24: MICROPROCESSOR REGISTER #5, BIT DESCRIPTION ................................................................................ 58
TABLE 25: MICROPROCESSOR REGISTER #6, BIT DESCRIPTION ................................................................................ 60
TABLE 26: MICROPROCESSOR REGISTER #7, BIT DESCRIPTION ................................................................................ 61
TABLE 27: MICROPROCESSOR REGISTER #8, BIT DESCRIPTION ................................................................................ 62
TABLE 28: MICROPROCESSOR REGISTER #9, BIT DESCRIPTION ................................................................................ 62
TABLE 29: MICROPROCESSOR REGISTER #10, BIT DESCRIPTION .............................................................................. 63
TABLE 30: MICROPROCESSOR REGISTER #11, BIT DESCRIPTION .............................................................................. 63
TABLE 31: MICROPROCESSOR REGISTER #12, BIT DESCRIPTION .............................................................................. 64
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