XRT83L38 Datasheet, PDF (21/91 Pages) Exar Corporation – OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
SIGNAL NAME
TQFP
PIN #
BGA
LEAD #
TYPE
DESCRIPTION
LOOP1_0 179 A10
LOOP0_0 180 C10
LOOP1_1 177 A11
LOOP0_1 178 B10
LOOP1_2 175 C11
LOOP0_2 176 D11
LOOP1_3 173 A12
LOOP0_3 174 B11
LOOP1_4
67
T7
LOOP0_4
68
U7
LOOP1_5
69
V7
LOOP0_5
70
V8
LOOP1_6
71
V9
LOOP0_6
72
U8
LOOP1_7
73
U9
LOOP0_7
74
R7
Loop-back Control Pins, Bits [1:0] Channel_[7:0]
I Loop-back Control bit 1, Channel _0
Loop-back Control bit 0, Channel _0
Loop-back Control bit 1, Channel _1
Loop-back Control bit 0, Channel _1
Loop-back Control bit 1, Channel _2
Loop-back Control bit 0, Channel _2
Loop-back Control bit 1, Channel _3
Loop-back Control bit 0, Channel _3
Loop-back Control bit 1, Channel _4
Loop-back Control bit 0, Channel _4
Loop-back Control bit 1, Channel _5
Loop-back Control bit 0, Channel _5
Loop-back Control bit 1, Channel _6
Loop-back Control bit 0, Channel _6
Loop-back Control bit 1, Channel _7
Loop-back Control bit 0, Channel _7
In Hardware mode, these pins control the Loop-Back mode for each
channel_n per the following table.
LOOP1_n LOOP0_n
MODE
0
0
Normal Mode No Loop-Back Channel_n
0
1
Local Loop-Back Channel_n
1
0
Remote Loop-Back Channel_n
1
1
Digital Loop-Back Channel_n
A[1]
179 A10
A[0]
180 C10
A[3]
177 A11
A[2]
178 B10
A[5]
175 C11
A[4]
176 D11
A[7]
173 A12
A[6]
174 B11
D[7]
67
T7
D[6]
68
U7
D[5]
69
V7
D[4]
70
V8
D[3]
71
V9
D[2]
72
U8
D[1]
73
U9
D[0]
74
R7
Microprocessor Address A[7:0] and Data Bus Pins D[7:0] - Host mode
These pins are microprocessor address and data bus pins. See “Microproces-
sor Interface Address Bus Pins - Host mode:” on page 13. and see “Micropro-
cessor Read/Write Data Bus Pins - Host mode” on page 12.
NOTE: These pins are internally pulled “Low” with a 50kΩ resistor.
17