XRT83L38 Datasheet, PDF (30/91 Pages) Exar Corporation – OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
The total cable loss at RLOS declaration is typically -52dB (-43dB + -9dB). A 3dB hysteresis was designed so
that transients will not trigger the RLOS to clear. Therefore, the RLOS will typically clear at a total cable
attenuation of -49dB. See Figure 9 for a simplified diagram.
FIGURE 9. SIMPLIFIED DIAGRAM OF EXTENDED RLOS MODE (E1 ONLY)
+3dB
-9dB
Normalized up to +45dB Max
Clear LOS
Declare LOS
+3dB
-9dB
Declare LOS
Clear LOS
Normalized up to +45dB Max
RECEIVE HDB3/B8ZS DECODER
The Decoder function is available in both Hardware and Host modes on a per channel basis by controlling the
TNEG_n/CODES_n pin or the CODES_n interface bit. The decoder function is only active in single-rail Mode.
When selected, receive data in this mode will be decoded according to HDB3 rules for E1 and B8ZS for T1
systems. Bipolar violations that do not conform to the coding scheme will be reported as Line Code Violation at
the RNEG_n/LCV_n pin of each channel. The length of the LCV pulse is one RCLK cycle for each code
violation. In E1mode only, an excessive number of zeros in the receive data stream is also reported as an error
at the same output pin. If AMI decoding is selected in single rail mode, every bipolar violation in the receive
data stream will be reported as an error at the RNEG_n/LCV_n pin.
RECOVERED CLOCK (RCLK) SAMPLING EDGE
This feature is available in both Hardware and Host modes on a global basis. In Host mode, the sampling
edge of RCLK output can be changed through the interface control bit RCLKE. If a “1” is written in the RCLKE
interface bit, receive data output at RPOS_n/RDATA_n and RNEG_n/LCV_n are updated on the falling edge of
RCLK for all eight channels. Writing a “0” to the RCLKE register, updates the receive data on the rising edge of
RCLK. In Hardware mode the same feature is available under the control of the RCLKE pin.
FIGURE 10. RECEIVE CLOCK AND OUTPUT DATA TIMING
R_DY
RCLK_R
RCLK_F
RCLK
RPOS
or
RNEG
R_HO
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