XRT83L38 Datasheet, PDF (72/91 Pages) Exar Corporation – OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
TABLE 36: MICROPROCESSOR REGISTER #129, BIT DESCRIPTION
D6
CLKSEL2 Clock Select Inputs for Master Clock Synthesizer bit 2:
R/W
0
In Host mode, CLKSEL[2:0] are input signals to a programma-
ble frequency synthesizer that can be used to generate a mas-
ter clock from an external accurate clock source according to
the following table;
MCLKE1 MCLKT1
kHz
kHz
2048
2048
2048
2048
2048
1544
1544
1544
1544
1544
2048
1544
8
X
8
X
16
X
16
X
56
X
56
X
64
X
64
X
128
X
128
X
256
X
256
X
CLKSEL2
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
CLKSEL1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
CLKSEL0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
MCLKRATE
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CLKOUT/
kHz
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
In Hardware mode, the state of these signals are ignored and
the master frequency PLL is controlled by the corresponding
Hardware pins.
D5
CLKSEL1 Clock Select inputs for Master Clock Synthesizer bit 1:
R/W
0
See description of bit D6 for function of this bit.
D4
CLKSEL0 Clock Select inputs for Master Clock Synthesizer bit 0:
R/W
0
See description of bit D6 for function of this bit.
D3
MCLKRATE Master clock Rate Select: The state of this bit programs the R/W
0
Master Clock Synthesizer to generate the T1/J1 or E1 clock.
The Master Clock Synthesizer will generate the E1 clock when
MCLKRATE = “0”, and the T1/J1 clock when MCLKRATE =
“1”.
D2
RXMUTE Receive Output Mute: Writing a “1” to this bit, mutes receive R/W
0
outputs at RPOS/RDATA and RNEG/LCV pins to a “0” state for
any channel that detects an RLOS condition.
NOTE: RCLK is not muted.
D1
EXLOS Extended LOS: Writing a “1” to this bit extends the number of R/W
0
zeros at the receive input of each channel before RLOS is
declared to 4096 bits. Writing a “0” reverts to the normal mode
(175+75 bits for T1 and 32 bits for E1).
D0
ICT
In-Circuit-Testing: Writing a “1” to this bit configures all the
R/W
0
output pins of the chip in high impedance mode for In-Circuit-
Testing. Setting the ICT bit to “1” is equivalent to connecting
the Hardware ICT pin 88 to ground.
68